Abstract
This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.
Highlights
In radio frequency integrated circuits (RFIC), the design of frequency synthesizers has been intensively discussed over the past few decades [1,2]
When the frequency synthesizer is far from the locked state, the charge pump (CP) and loop filter will be controlled by the module to set a large loop bandwidth to accelerate locking, while the frequency synthesizer is close to the locked state, the loop bandwidth is adjusted to a lower value to obtain better phase noise and spur performance
According to Equation (13), the adaptive loop bandwidth control (ALBC) module designed in this paper automatically controls Icp and RC in the loop filter to set the loop bandwidth to a higher value when the Phase-locked loop (PLL) is far away from the locked state to speed up the locking process, while lower the loop bandwidth when the PLL is close to the locked state to obtain better phase noise performance
Summary
In radio frequency integrated circuits (RFIC), the design of frequency synthesizers has been intensively discussed over the past few decades [1,2]. To accelerate the locking speed, there are three main technologies namely dynamic loop bandwidth [7,8,9,10,11,12], fractional-N frequency division [6,13,14,15], feed-forward preset [16,17,18], and the emerging all-digital PLL (AD-PLL) [15,19]. Prior state-of-the-art, such as digital frequency detector with switchable bandwidth [11], auxiliary phase detector [9] and double loop filter [8] etc., all require circuit modification of the phase-frequency detector (PFD), CP or other analog modules with a potential risk of phase noise deterioration. By only adding a very compact, low power digital circuit without changing any key module design of the PFD, CP, and VCO, etc., we can speed up the lock process of about 30%.
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