適用於MB-OFDM超寬頻系統Group-1和Group-3子頻帶之頻率合成器設計

Abstract

The frequency synthesizer is an important role of the transceivers in the wireless communication systems. Today, various kinds of standard specifications are proposed for the communication systems. A different specification would lead to different frequency synthesizer's design. This thesis takes into account the frequency synthesizer design for the multi-band orthogonal-frequency-division-multiplexing (MB-OFDM) ultra-wideband (UWB) system, especially for the needs of Group-1 and the Group-3 sub-bands, in which there are six frequency outputs. The different designs of frequency synthesizers will lead to different circuit area and power consumption. Therefore, how to reduce the complexity of the electric circuit integration while achieving the same function is the design key point. In this thesis, the frequency synthesizer was fabricated in TSMC’s 0.18m 1P6M CMOS process. Our proposed frequency synthesizer is composed of one phase-locked loop (PLL), two multiplexers, two dividers, and two single-sideband (SSB) mixers. The PLL is operated at 6336 MHz with a 264 MHz reference input. The PLL has to provides quadrature outputs for driving the SSB mixers, so a quadrature voltage-controlled oscillator (QVCO) is necessary. There are two types of output loads for the SSB mixers; one is a resistive type for the operation frequency 2640 MHz; another is an LC-resonant type for those operation frequencies are 7656, 7128, 6600, 4488, 3960, and 3432 MHz. The PLL in the proposed UWB frequency synthesizer uses a second-order low pass filter (LPF). In the past, PLLs may utilize off-chip LPFs for the design flexibility consideration. This way can help to reduce the chip fail problem, but it will possibly cause more noises in the PLL. In this thesis, we use the on-chip LPF design that can have lower noise and less pump current level. Therefore, the power consumption of the charge pump circuit can be reduced. To consider the area consumption of the whole frequency synthesizer, the use with capacitive multiplication technique on the LPF can make the capacitor area small and the jitter performance of the QVCO improved. The capacitive multiplication technique is implemented with the help of an OP amplifier. The primary contribution of this thesis is the integration of a PLL, which consists of a phase frequency detector, a charge pump, an on-chip low pass filter, a QVCO and four dividers. The charge pump is implemented by a rail-to-rail error amplifier to overcome the process variation and the current matching problem. The low pass filter use capacitive multiplication technique with a smaller capacitance value and thus the chip area can be reduced. Considering the cooperative use of the SSB mixers in our proposed frequency synthesizer, a novel quadrature TSPC divide-by-3 circuit has been proposed. The total chip area is 1.3 mm × 1.3 mm. The output power is -7.63 dBm. The measured average phase noises of the PLL is -86.07 dBc/Hz at 100kHz offset from the center frequency. That of -102.23 dBc/Hz and -127.31 dBc/Hz at 1 MHz and 10 MHz offset frequencies, respectively, from the center frequency can be obtained. The power consumption is 32mW and the reference spur is -49.4 dBm. The post-layout simulation has been done for our proposed frequency synthesizer. The two SSB mixers respectively with an RC load and an LC load totally consumes the power consumption of 17.04 mW. The two multiplexers respectively with the bi-ways and tri-ways in power consumption are 6.92 mW. The total power consumption is 65.08mW and the vdd is 1.5V. The layout area is 1.2 mm × 1.15 mm without PAD.