FPGA Structure Research Articles

Data repair accelerating scheme for erasure-coded storage system based on FPGA and hierarchical parallel decoding structure

Data repair accelerating scheme for erasure-coded storage system based on FPGA and hierarchical parallel decoding structure

Method of Synthesis of Devices for Parallel Stream Calculation of Scalar Product in Real Time

A graph scheme of a generalized algorithm for parallel stream calculation of the scalar product was developed. The proposed algorithm uses the same type of operations for forming a partial product that is calculated starting from the lowest digits of the multipliers. The developed algorithm of parallel stream calculation of the scalar product is performed with the use of operations for forming partial products, calculating the macro-partial product, and adding it to the partial result shifted to the right by the number of digits that were used in the formation of partial products. It is suggested that the development of FPGA structures of devices for parallel stream calculation of the scalar product be carried out according to the following principles: use of the same type of conveyor steps; performing calculations based on addition, inversion, and shift operations; performing the calculation of the scalar product as a single operation; regularity and localization of connections between conveyor steps; coordination of the duration of the conveyor time with the time of data input and the time of output of calculation results; space-time parallelization of the process of calculating the scalar product. The algorithm and structure of the parallel stream device for calculating the scalar product with direct formation of partial products based on the analysis of one order of multipliers, which ensures operation with the smallest conveyor cycle, has been developed. The algorithm and structure of the parallel stream device for calculating the scalar product with the formation of partial products for the sum of two pairs of products with the analysis of one order of multipliers, which is advisable to use for a small number of operands, have been developed. The algorithm and structure of a parallel stream device for calculating the scalar product with the formation of partial products according to the modified Booth algorithm have been developed, which ensures a reduction in equipment costs when processing operands with n≥24 bits. The algorithm and structure of the device for calculating the scalar product with the formation of group partial products have been developed, which provides the lowest equipment costs in the case of n=8 for N>8. A method for the synthesis of FPGA devices for parallel stream calculation of the scalar product in real-time has been developed. The proposed method ensures high efficiency of the use of the equipment due to the selection of the algorithm for the formation of partial products and the structure of the device from the list of developed ones and the coordination of the cycle of the conveyor of the selected structure with the time of arrival of input data.

Тестування на проникнення компонентів FPGA як сервісу для забезпечення кібербезпеки

The subject of study in this article is modern penetration testing technologies, in which the test object is a platform with access to FPGA resources. The goal of this work is to improve modern methods of penetration testing of services that provide FPGA as a Service, to identify vulnerabilities, the elimination of which increases the level of security of services and increases the level of user trust in such services. Task: to analyze possible threats of FPGA as a Service platforms; analyze the structure of FPGA as a Service platforms; analyze options for using the penetration testing standard; and offer key components for ensuring cyber security of FPGA as a Service platforms. According to the tasks, the following results were obtained. A study of the cyber security problems of FPGA as a Service platforms was conducted, and a set of components for ensuring the cybersecurity of FPGA as a Service platforms was proposed. An analysis of modern cybersecurity threats of FPGA as a Service platforms was carried out. The possibility of applying the penetration testing standard to FPGA services is considered. Regular audits and penetration testing are key elements of a cybersecurity strategy and help maintain customer and user trust in FPGA services. A set of components for ensuring cybersecurity of FPGA as a Service platforms is proposed, which corresponds to modern threats. The complex includes activities such as regular software updates, security monitoring and analysis, audit and penetration testing, compliance with security standards, and staff training. Conclusions. The main contribution and scientific novelty of the obtained results is that a study of the possibilities of penetration testing was conducted, where the test object is a platform with access to FPGA resources. As in many other areas, ensuring the cybersecurity of FPGA as a Service platforms is a complex task, where ignoring any component can lead to critical consequences. Applying only penetration testing is not enough; therefore, a comprehensive list of cybersecurity measures for FPGA as a Service platforms is provided.

Highly Responsive, Miniaturized Methane Telemetry Sensor Based on Open-Path TDLAS

This paper proposes the design of a highly responsive, compact, non-contact methane telemetry sensor, employing the open-path tunable diode laser absorption spectroscopy (OP-TDLAS) technology. The sensor uses the dual-core structure of FPGA and ARM to achieve high-speed methane telemetry at 100 KHz repeated modulation frequency for the first time with a non-cooperate target, and a higher gas responsive time of 1.8 ms was achieved than previously reported. Moreover, the optical system (L × W × H: 68.8 × 52 × 62.7 mm) and the electronic system (L × W: 70 × 50 mm) make the sensor more compact. Methane gas samples of varying integral concentrations were examined at a distance of 20 m. The amplitude of the absorption peaks was subjected to a linear fit with the standard concentration values, resulting in a robust linear correlation coefficient (R2 = 0.998). Notably, despite the compact form factor of the methane sensor, it demonstrated commendable stability in gas concentration detection, offering a minimum detection limit of 43.14 ppm·m. Consequently, this highly responsive and compact methane sensor, with its open-path feature, is apt for integration into a variety of applications requiring such attributes. These include handheld telemetry devices, Unmanned Aerial Vehicle (UAV) gas detection systems, vehicle mounted gas detection, and laser gas radar.

Trigger based on fuzzy logic for the detection of neutrino-induced extensive air showers in water-Cherenkov detectors

A fuzzy logic trigger is an alternative approach to triggering a discrete cosine transform or a trigger based on artificial neural networks developed for the surface detector of the Pierre Auger Observatory. The aim of the article is to report on the development of estimators that would allow one distinguishing the signal profiles from the Auger photomultipliers of the water-Cherenkov detectors originating from the neutrino-induced atmospheric showers with a high background of the proton showers. Fuzzy Logic Toolbox provides MATLAB functions, apps, and a Simulink block for analyzing, designing, and simulating systems based on fuzzy logic. The next step is to implement trace recognition algorithms in the FPGA structure to generate a real-time trigger with reasonable use of FPGA resources and with sufficient time margin for 120 MHz sampling. The fuzzy logic trigger will support existing triggers in the Auger surface detector but is optimized to identify neutrino-generated showers. The next step in our research is the simulation of electromagnetic and hadronic cascades in the atmosphere, the propagation of Cherenkov light in the water detector, and the digitalization of the signals in the ADC if the preliminary results obtained from the artificially generated profiles are satisfactory.

Development of a model for determining the necessary FPGA computing resource for placing a multilayer neural network on it

In this paper, the object of the research is the implementation of artificial neural networks (ANN) on FPGA. The problem to be solved is the construction of a mathematical model used to determine the compliance of FPGA computing resources with the requirements of neural networks, depending on their type, structure, and size. The number of its LUT (Look-up table – the basic FPGA structure that performs logical operations) is considered as a computing resource of the FPGA. The search for the required mathematical model was carried out using experimental measurements of the required number of LUTs for the implementation on the FPGA of the following types of ANNs: – MLP (Multilayer Perceptron); – LSTM (Long Short-Term Memory); – CNN (Convolutional Neural Network); – SNN (Spiking Neural Network); – GAN (Generative Adversarial Network). Experimental studies were carried out on the FPGA model HAPS-80 S52, during which the required number of LUTs was measured depending on the number of layers and the number of neurons on each layer for the above types of ANNs. As a result of the research, specific types of functions depending on the required number of LUTs on the type, number of layers, and neurons for the most commonly used types of ANNs in practice were determined. A feature of the results obtained is the fact that with a sufficiently high accuracy, it was possible to determine the analytical form of the functions that describe the dependence of the required number of LUT FPGA for the implementation of various ANNs on it. According to calculations, GAN uses 17 times less LUT compared to CNN. And SNN and MLP use 80 and 14 times less LUT compared to LSTM. The results obtained can be used for practical purposes when it is necessary to make a choice of any FPGA for the implementation of an ANN of a certain type and structure on it

Hardware Software Co-Design for Impact Localization using Hybrid Laminates

Impact detection using piezoelectric sensors is an actual and widespread research field. The current work provides an approach for a real-time realization of an impact detection system using deep learning methods. For realization a hardware software co-design approach is used utilizing hardware acceleration by a continuous pipelining FPGA structure. The concept describes the hardware software partitioning of the underlying functions and the methodology for ensuring continuous data processing and the associated real-time capability. The behavior of the hardware is realized with the help of a finite state machine and thus the correctness of the data is ensured and the impact identification is realized. The results show the real-time capability as well as a reasonable resource utilization of the FPGA design.

Enhancing the performance of asymmetric architectures and workload characterization using LSTM learning algorithm

Asymmetric multiple core architectures are becoming increasingly popular because of their QoS, energy efficiency, and high performance. Because of the heterogeneous piping layout and execution procedure, the overall system performance is highly influenced by workload characterization becomes a difficult issue. Recently, it has become vital to create a performance evaluator for faster response FPGA structures. With the embedded computerized visual hardware resources (e.g. GPUs, FPGAs, and multi-core CPUs) and its associated software manages this heterogeneous system design is tough for the researchers. A thorough analysis of the performance of run-time and various embedded kernels' energy efficiencies to assist developers in determining which embedded substrate is best for their project. To solve these challenges, resource-based prediction models are developed for FPGA-SoC relying on the characterization of intellectual workload, and its performance is thoroughly examined. Xilinx FPGA frameworks are used to run a variety of real-time applications that perform workloads depending on projected processing cores. When compared to existing Ml classifiers, this LSTM predictor achieves a mean of 96% of the experimental findings and also improves energy efficiency.

An Analysis of the Impact of Gating Techniques on the Optimization of the Energy Dissipated in Real-Time Systems

The paper concerns research on electronics-embedded safety systems. The authors focus on the optimization of the energy consumed by multitasking real-time systems. A new flexible and reconfigurable multi-core architecture based on pipeline processing is proposed. The presented solution uses thread-interleaving mechanisms that allow avoiding hazards and minimizing unpredictability. The proposed architecture is compared with the classical solutions consisting of many processors and based on the scheme using one processor per single task. Energy-efficient task mapping is analyzed and a design methodology, based on minimizing the number of active and utilized resources, is proposed. New techniques for energy optimization are proposed, mainly, clock gating and switching-resources blocking. The authors investigate two main factors of the system: setting the processing frequency, and gating techniques; the latter are used under the assumption that the system meets the requirements of time predictability. The energy consumed by the system is reduced. Theoretical considerations are verified by many experiments of the system’s implementation in an FPGA structure. The set of tasks tested consists of programs that implement Mälardalen WCET benchmark algorithms. The tested scenarios are divided into periodic and non-periodic execution schemes. The obtained results show that it is possible to reduce the dynamic energy consumed by real-time applications’ meeting their other requirements.

ПІДХІД ДО НЕЕКВІВАЛЕНТНОГО СТЕГАНОГРАФІЧНОГО ВБУДОВУВАННЯ ДОДАТКОВИХ ДАНИХ В ПРОГРАМНИЙ КОД БЛОКІВ LUT FPGA

Purpose. To increase the effective volume of stego containers in the FPGA program code. To achieve this purpose, an additional procedure of non-equivalent transformations of FPGA program code is added. Non-equivalent transfor-mations complement the traditional procedure of equivalent transformations of program code. The joint use of these two types of transformations leads to the achievement of the purpose of this paper. Methodology. The steganographic ap-proach is used to covertly embed additional data into the FPGA chip program code. In this case the FPGA program code is a stego container. The stego container embedding procedure is used to perform hidden monitoring of the FPGA program code. For this purpose, monitoring data is embedded into the program code and secretly stored there. The tradi-tional approach to steganographic embedding in FPGA program code is based on the use of equivalent transformations of the program code. Such transformations do not change the target function of the program code or the operation of the FPGA chip. However, the traditional approach provides a relatively small effective volume of the stego container. This leads to the fact that it is usually possible to steganographically store only control data for one type of monitoring. It is proposed to additionally use a non-equivalent approach to steganographic embedding of data into the FPGA program code. Such transformations, despite their non-equivalence, do not change the target function of the program code. This is achieved by applying transformations to the program code of units that perform arithmetic operations on approximate data. For arithmetic operations on approximate data there is often a requirement that the operands and the result are the same size. To satisfy this requirement the complete result of the operation is computed first. After that some bits of the result are discarded and rounding is performed. It is proposed to allocate elementary LUT units in the FPGA structure, which participate only in the calculation of discarded bits (and do not participate in the calculation of the remaining bits). Program codes of such LUTs can be non-equivalently changed during steganographic embedding. Distortion of the FPGA program code of such units does not distort the behavior of the FPGA chip. This is a consequence of the fact that such LUTs are not involved in the formation of the discarded bits. Results. We have developed software that, together with Intel Quartus CAD system, extracts detailed information about an FPGA project. This information includes the structure of the circuit in the project and the program codes of the units of this circuit. An application has also been developed that uses this information to determine non-equivalent steganographic resources. With the help of the devel-oped software, an experimental estimation of the additional volume of the stego container is performed. Originality. An approach to the use of non-equivalent transformations of the program code of FPGA chips for steganographic embed-ding of additional data is proposed. This approach is proposed to be used together with the traditional approach, which is based on equivalent transformations of the program code. Practical value. The steganographic embedding approach proposed in this paper allows increasing the effective volume of the stego container in the FPGA program code. By ap-plying this approach, it becomes possible to secretly store monitoring data of several types of monitoring in FPGA stego containers. References 10, figures 2.

Logic Synthesis Strategy Oriented to Low Power Optimization

The article presents a synthesis strategy focused on low power implementations of combinatorial circuits in an array-type FPGA structure. Logic functions are described by means of BDD. A new form of the SWitch activity BDD diagram (SWBDD) is proposed, which enables a function decomposition to minimize the switching activity of circuits. The essence of the proposed idea lies in the proper ordering of the variables and cutting the diagram, ensuring the minimization of switching in the combination circuit. This article contains the results of experiments confirming the effectiveness of the developed concept of decomposition. They were performed on popular benchmarks using academic and commercial synthesis systems.

Design of a Reconfigurable Information Collection and Identification System for Packages Storage and Checkout

With the continuous and rapid development of e-commerce, the requirements of logistics informatization are also increasing. At present, the barcode collection and identification device used in the operation of packages storage and checkout is generally based on ASIC chip, which is not fast enough. Therefore, this paper proposes a reconfigurable information acquisition and identification system, which is applied to the operation of package storage and delivery. This system uses FPGA + ARM architecture to realize the functions of identifying, storing and uploading the barcode information on the outer surface of the package to the host computer through UDP protocol. Because the parallel operation structure of FPGA is used to design the barcode image processing accelerator circuit, the data processing capacity of the soft core processor is reduced, and the recognition speed of the system is improved as a whole. The test shows that this system is faster and more accurate than the package barcode information recognition device based on ASIC technology.

FPGA-based Dual Core TRNG Design Using Ring and Runge-Kutta-Butcher based on Chaotic Oscillator

Despite the fact that chaotic systems do not have very complex circuit structures, interest in chaotic systems has increased considerably in recent years due to their interesting dynamic properties. Thanks to the noise-like properties of chaotic oscillators and the ability to mask information signals, great efforts have been made in recent years to develop chaos-based TRNG structures. In this study, a new chaos-based dual entropy core TRNG with high operating frequency and high bit generation rate was realized using 3D Pehlivan-Wei Chaotic Oscillator (PWCO) structure designed utilizing RK-Butcher numerical algorithm on FPGA and ring oscillator structure. In the FPGA-based TRNG model of the system, 32-bit IQ-Math fixed-point number standard is used. The developed model is coded using VHDL. The designed TRNG unit was synthesized for Virtex-7 XC7VX485T-2FFG1761 chip produced by Xilinx. Then, the statistics of the parameters of FPGA chip resource usage and unit clock speed were examined. The data processing time of the TRNG unit was achieved by using the Xilinx ISE Design Tools 14.2 simulation program, with a high bit production rate of 437.043 Mbit/s. In addition, number sequences obtained from FPGA-based TRNG were subjected to the internationally valid statistical NIST 800-22 Test Suite and all the randomness tests of NIST 800-22 Test Suite were successful.

Electromagnetic Occlusion Algorithm Based on FPGA and Panel Grouping and Its Optimization

With the development of digital signal processing and advanced algorithms, real‐time signal processing based on FPGA and DSP is suitable for high‐speed radar signal processing. With the rapid development of science and technology, war has entered the information age guided by high technology, and advanced science and technology has played a vital role in the trend of war. In recent years in the modern war, many countries invest a lot of research effort on the stealth technology, and advanced stealth technology can use a variety of technical means to alter or weaken the feature information of the target, confuse the enemy radar detection system effectively, reduce the chance of being detected to the largest extent, and prolong the lifecycle of aircraft and weapons. This research mainly discusses the electromagnetic occlusion algorithm and its optimization based on FPGA and panel grouping. The FPGA model selected for this study is XC6VLX240T‐1FF1156I. Because the amount of data processed here is not very large, the cache part directly uses the on‐chip storage resources of the FPGA, and the AD device is used to perform analog‐to‐digital/digital‐to‐analog conversion on the signal and perform digital up‐down conversion. For a facet, it is necessary to first verify whether it is a bright facet and set the flag to mark it, then the facet needs to be occluded with the triangular facet marked as a bright facet, and all bright facets that have been marked need to be traversed. Open MP parallelization of the occlusion algorithm is as follows: The physical optics method is used to calculate the target RCS, and the focus of parallelism is placed on the part with a large amount of calculation. When using Open MP to design a program on a multicore computer, each group is assigned a thread to give full play to the core computing power. The total field is scattered and superimposed by each surface element. This part uses the parallel processing mode of Open MP, which allows the panel judgment in the group to be carried out at the same time. This part requires schedule to allocate resources and use different parallel mechanisms for different calculations to optimize debugging. In the angular range where there is multiple scattering at 0° ≤ φ ≤ 90°, the calculation results and the measurement results are in good agreement, and when the two planes are simulated with 1820 triangular faces, the fast multiple scattering in this paper only needs 4 minutes. This research has realized the general radar signal processing method based on FPGA structure, and the design has important engineering realization significance.

Efficient algorithm design on hybrid CPU-FPGA architecture for high performance computing

Heterogeneous multi-core processors aim at overall performance improvement of computations for applications in the field of computing. It employs cores with varying capabilities to achieve high performance computation. This paper proposes a hybrid structure of CPU and FPGA (HCF) heterogeneous, hard and soft-core custom processor. Algorithms have been proposed for efficient utilisation of the proposed hybrid processor to work as a platform of work for the software demanding high speed and performance metrics. The evaluation for all the algorithm were carried out in zybo board belonging to zynq 7010 family of all programmable system on chip FPGA board, with Xilinx vivado 2014.4 as the development software. Experimental results prove that the efficiency of the designed hybrid processor with efficient task based scheduling algorithm yields a 53% increase in the speed of execution with multi-threading and 52% performance improvement by top level pipelining.

Efficient algorithm design on hybrid CPU-FPGA architecture for high performance computing

Heterogeneous multi-core processors aim at overall performance improvement of computations for applications in the field of computing. It employs cores with varying capabilities to achieve high performance computation. This paper proposes a hybrid structure of CPU and FPGA (HCF) heterogeneous, hard and soft-core custom processor. Algorithms have been proposed for efficient utilisation of the proposed hybrid processor to work as a platform of work for the software demanding high speed and performance metrics. The evaluation for all the algorithm were carried out in zybo board belonging to zynq 7010 family of all programmable system on chip FPGA board, with Xilinx vivado 2014.4 as the development software. Experimental results prove that the efficiency of the designed hybrid processor with efficient task based scheduling algorithm yields a 53% increase in the speed of execution with multi-threading and 52% performance improvement by top level pipelining.

Dynamic Visual Communication Image Framing of Graphic Design in a Virtual Reality Environment

This paper explores dynamic visual communication image framing for graphic design based on virtual reality algorithms; it defines corresponding feature representations by delineating layers of pixels, elements, relationships, planes, and applications; and it investigates methods for quantifying geometric features, perceptual features, and style features. The contents include extraction methods for element colors, calculation methods for layout perceptual features and color-matching perceptual features, and pairwise comparison methods for style features. By overfitting the distribution of geometric features in the data, the model can predict the probability density distribution of features such as element position and color under specific conditions to support the generation of flat images. To construct a prediction model, the sampling method of features, the model optimization method, and the data learning strategy are investigated. This thesis involves the design and implementation of a lossless/near-lossless compression system for high-frame-rate gaze camera image data, which is faced with the technical problems of high fidelity and strong real-time and reliable compression. The image single-frame lossless/near-loss-free compression ratio is generally low, and the compression ratio can be improved by using the correlation between image frames. In this paper, we study the application of lossless compression between image frames, the efficient computing structure of FPGA, and an onboard compression system.

FPGA-accelerated textured surface defect segmentation based on complete period Fourier reconstruction

Real-time detection of surface defects in high-generation, large-size Liquid Crystal Display (LCD) panels is a serious challenge for both image algorithms and processing speed. For the defect detection of Thin Film Transistor-Liquid Crystal Display (TFT-LCD) images, effectively processing the periodic texture composed of gate lines and data lines is a prerequisite for the success of the algorithm. The traditional one-dimensional Fourier reconstruction algorithm uses a filter-based method to remove most of the texture, but due to the spectral leakage problem, the image boundary cannot be effectively processed. The compensation based on the period extension introduces a more complex ringing effect at the image connection. Starting from the implicit periodic principle of Fourier transform, we propose a strategy of complete period truncation based on subpixel period, which completely eliminates the boundary texture. Furthermore, we fully exploit the potential of parallel execution of the algorithm, resampling the liquid crystal segments truncated in the complete period to an integer power length of 2. The FPGA structure of one-dimensional Fourier reconstruction defect segmentation algorithm with dual-task parallelism and two-pixel parallelism is designed and the calculation bandwidth of 500 MB/s can be realized at 125-MHz clock frequency. We demonstrate the superiority of the proposed method qualitatively and quantitatively. The one-dimensional Fourier reconstruction algorithm based on the complete period truncation can effectively detect various defects such as spots, scratches, fibers and dirt, and the false-positive rate of defects has been reduced by half. The resampling-based Fourier transform speeds up the computational process and the FPGA parallel acceleration architecture is three times faster than comparable server CPUs, reducing the scan detection time of the entire 8.5-generation LCD panel to 8.5 s.

GASIM: The Gate Array Graphical Simulator for FPGA Architecture Learning

Field Programmable Gate Arrays, also called FPGA, are the main contemporary tool for digital systems learning and development. Its benefits are more than evident, but also are its internal complexity. The widespread use of FPGA devices has created a necessity for understanding the inner logic using diagrams or theoretical explanations. This paper presents an innovative approach for FPGA basic architecture learning called GASIM. A conceptually complete model for a simple but general 2-D graphical FPGA has been designed and implemented in such a way that is easy to understand, aesthetically appealing from the student’s point of view, and also easy to use by any teacher. The aim of this kind of design is to fill the conceptual gap we have found while teaching FPGA based courses. The final tool is a 2-D modular graphical library for a standalone logic simulator that not only allows teachers and students to program an FPGA model and simulate every aspect of its internal logic complexities but also to construct their own limited, but complete FPGA structure using drag and drop graphical modules and programmable interconnections. Our study provides a technical description of the tool, and our first results in the classroom.

Methods of Improving Time Efficiency of Decomposition Dedicated at FPGA Structures and Using BDD in the Process of Cyber-Physical Synthesis

Physical systems may be carried out in both hardware and software. Hardware is based on implementing appropriate logic functions in FPGA structures connected with a physical layer of cyber-physical systems (CPSs). Effective technology mapping of these functions in FPGA structures is directly connected with logic synthesis. Thus, in the case of CPSs, we can talk about cyber-physical synthesis. The effectiveness of this synthesis is key from the point-of-view of designing CPSs. This paper focuses on the methods aiming at shortening synthesis time of circuits carried out in FPGA circuits. The proposed synthesis methods stem from an original way of a function representation enabling to quick search for appropriate decompositions. This paper presents a series of original methods. They include enabling for a quick relocating of variables between bound and free sets, time effective and multilevel technology mapping of multi-output function, and techniques of quick efficiency assessing of technology mapping taking non-disjoint decomposition into account. The methods are the basis of the algorithms implemented in the author's synthesis tools such as dekBDD and MultiDec. The effectiveness of the proposed methods was proved via experiments. The main contribution of the paper in the area of cyber-physical synthesis is proposing effective methods of carrying out a hardware layer cyber-physical synthesis that uses the FPGA circuits.