Abstract
The article presents a synthesis strategy focused on low power implementations of combinatorial circuits in an array-type FPGA structure. Logic functions are described by means of BDD. A new form of the SWitch activity BDD diagram (SWBDD) is proposed, which enables a function decomposition to minimize the switching activity of circuits. The essence of the proposed idea lies in the proper ordering of the variables and cutting the diagram, ensuring the minimization of switching in the combination circuit. This article contains the results of experiments confirming the effectiveness of the developed concept of decomposition. They were performed on popular benchmarks using academic and commercial synthesis systems.
Highlights
Logic synthesis aimed at minimizing power consumption is currently one of the most important problems in the design of energy-saving digital circuits
It was decided to compare with the leading synthesis tool ABC [27]
The work [44] discusses the appropriate scripts for the ABC system: “Baseline” as the basic one, and “PowerMap” and “PowerDC” as the scripts aimed at reducing power consumption
Summary
Logic synthesis aimed at minimizing power consumption is currently one of the most important problems in the design of energy-saving digital circuits. The problem of heat dissipation began to play a dominant role; resulting in the need to reduce power consumption. Minimizing power consumption should be sought at every level of circuit design. The stage of the system synthesis, at which the greatest limitations of power consumption can be found, undoubtedly depends on the specificity of the designed system. The greatest benefits are to be expected when looking for a reduction in power losses at the highest design levels [1]. At the highest design level is it possible to anticipate the temporary shutdown of the modules of the designed hardware and software system, which undoubtedly significantly reduces the total power of losses
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