Methods of Improving Time Efficiency of Decomposition Dedicated at FPGA Structures and Using BDD in the Process of Cyber-Physical Synthesis

Abstract

Physical systems may be carried out in both hardware and software. Hardware is based on implementing appropriate logic functions in FPGA structures connected with a physical layer of cyber-physical systems (CPSs). Effective technology mapping of these functions in FPGA structures is directly connected with logic synthesis. Thus, in the case of CPSs, we can talk about cyber-physical synthesis. The effectiveness of this synthesis is key from the point-of-view of designing CPSs. This paper focuses on the methods aiming at shortening synthesis time of circuits carried out in FPGA circuits. The proposed synthesis methods stem from an original way of a function representation enabling to quick search for appropriate decompositions. This paper presents a series of original methods. They include enabling for a quick relocating of variables between bound and free sets, time effective and multilevel technology mapping of multi-output function, and techniques of quick efficiency assessing of technology mapping taking non-disjoint decomposition into account. The methods are the basis of the algorithms implemented in the author's synthesis tools such as dekBDD and MultiDec. The effectiveness of the proposed methods was proved via experiments. The main contribution of the paper in the area of cyber-physical synthesis is proposing effective methods of carrying out a hardware layer cyber-physical synthesis that uses the FPGA circuits.