FPGA Circuit Research Articles

Static power model for CMOS and FPGA circuits

In Ultra-Low-Power (ULP) applications, power consumption is a key parameter for process independent architectural level design decisions. Traditionally, time-consuming Spice simulations are used to measure the static power consumption. Herein, a technology-independent static power estimation model is presented, which can estimate static power with reasonable accuracy in much less time. It is shown that active area only is not a good indicator for static power consumption, hence in this model, the effects of transistor sizing, transistor stacking, gate boosting and voltage change are considered. The procedure to apply this model to processors and FPGAs is demonstrated. Across different process technologies, compared to traditional spice simulation, this model can estimate the static power consumption of processor with an error of 1%–4%, while static power consumption of an FPGA system with an error of 1%–15%.

A Highly Configurable High-Level Synthesis Functional Pattern Library

FPGA has recently played an increasingly important role in heterogeneous computing, but Register Transfer Level design flows are not only inefficient in design, but also require designers to be familiar with the circuit architecture. High-level synthesis (HLS) allows developers to design FPGA circuits more efficiently with a more familiar programming language, a higher level of abstraction, and automatic adaptation of timing constraints. When using HLS tools, such as Xilinx Vivado HLS, specific design patterns and techniques are required in order to create high-performance circuits. Moreover, designing efficient concurrency and data flow structures requires a deep understanding of the hardware, imposing more learning costs on programmers. In this paper, we propose a set of functional patterns libraries based on the MapReduce model, implemented by C++ templates, which can quickly implement high-performance parallel pipelined computing models on FPGA with specified simple parameters. The usage of this pattern library allows flexible adaptation of parallel and flow structures in algorithms, which greatly improves the coding efficiency. The contributions of this paper are as follows. (1) Four standard functional operators suitable for hardware parallel computing are defined. (2) Functional concurrent programming patterns are described based on C++ templates and Xilinx HLS. (3) The efficiency of this programming paradigm is verified with two algorithms with different complexity.

Parallel Implementation of Nios Ii Multiprocessors, Cepstral Coefficients of Mel Frequency and MLP Architecture in Fpga: the Application of Speech Recognition

Speech processing in real time requires the use of fast, reconfigurable electronic circuits capable of handling large amounts of information generated by the audio source. This article presents hardware implementations of a multilayer perceptron (MLP) and the MFCC algorithm for speech recognition. These algorithms have been implemented in hardware and tested in an on-board electronic card based on a reconfigurable circuit (FPGA). We also present a comparative study between several architectures of MLP and with the literature on the level of costs with regard to the surface of silicon, the speed and the computing resources required. Following the FPGA circuit modification, we created NIOSII processors to physically implement the architecture of ANN-type MLPs and MFCC speech recognition algorithms and perform real-time speech recognition functions.

A high performance scalable fuzzy based modified Asymmetric Heterogene Multiprocessor System on Chip (AHt-MPSOC) reconfigurable architecture

This Ensuing generation of FPGA circuit tolerates the combination of lot of hard and soft cores as well as devoted accelerators on a chip. The Heterogene Multi-Processor System-on-Chip (Ht-MPSoC) architecture accomplishes the requirement of modern applications. A compound System on Chip (SoC) system designed for single FPGA chip, and that considered for the performance/power consumption ratio. In the existing method, a FPGA based Mixed Integer Programming (MIP) model used to define the Ht-MPSoC configuration by taking into consideration the sharing hardware accelerator between the cores. However, here, the sharing method differs from one processor to another based on FPGA architecture. Hence, high number of hardware resources on a single FPGA chip with low latency and power targeted. For this reason, a fuzzy based MIP and Graph theory based Traffic Estimator (GTE) are proposed system used to define New asymmetric multiprocessor heterogene framework on microprocessor (AHt-MPSoC) architecture. The bandwidths, energy consumption, wait and transmission range are better accomplished in this suggested technique than the standard technique and it is also implemented with a multi-task framework. The new Fuzzy control-based AHt-MPSoC analysis proves significant improvement of 14.7 percent in available bandwidth and 89.8 percent of energy minimized to various traffic scenarios as compared to conventional method.

Library Characterization of Arithmetic Circuits for Reliability-Aware Designs in SRAM-Based FPGAs

Designing an application in hardware under inversely competing constraints such as area and performance with different objective functions such as power consumption and reliability of the circuits is a cumbersome task. Having different versions of the same resource type during the design process may ease this burden since there can be several alternative resources to meet the given constraints. In this paper, we characterize a library of some commonly used arithmetic circuits in FPGAs in terms of the speed, area, power consumption, and vulnerability to error propagation as the reliability parameter. Specifically, we implemented four well-known adders and two multipliers in an SRAM-based FPGA that is a part of Xilinx’s Zynq-7000 SoC platform. We then injected errors to the configuration bits of the circuits to evaluate the error propagation. The results show that different versions of the same resources can have different reliability values in addition to the area, latency, and power values.

CAPACITIVE COMPLEXITY OF DETERMINING GCD IN THE SHOR S ALGORITHM

The article analyzes the results of finding the period r of the function y = axmodM (a is a random number) which is used in the Shor's factorization algorithm for quantum computers. The module M is the product of two primes p and q. The article analyzes the solutions r obtained for various a, for which the capacitive complexity H of finding the greatest common divisor GCD(ar/2 + 1, M) is the least. A digital quantum computer is a classic processor and its digital quantum coprocessor. A digital quantum coprocessor with hundreds and thousands of digital qubits can be implemented in one programmable logic integrated circuit FPGA. In the Shor’s algorithm, the factorization problem of the number M reduces to the problem of determining the period r of the function y. It is known that GCD(ar/2 + 1, M) can be a divisor of the number M The task of the quantum coprocessor in implementing the Shor’s algorithm is to find the period r. After that it is necessary to find the GCD. Since for random a the problem of finding the period r has many solutions, these solutions can be compared by the value of one of the arguments when finding the GCD - the number ar / 2 . In this case, H = (rlog2a)/2 is taken for analysis. It approximately represents the bit depth of binary codes that a classic computer will have to process when determining the GCD. H can vary over a wide range from tens to thousands of bits even for small values of M. In this research the period r, which ensures the least complexity of the subsequent task of finding the GCD, is most often a solution for a = 3 and a = 2, but it can also occur often with other values of a. To clarify the revealed patterns, especially for large M, it is necessary to conduct additional research.

Real-time tracing FPGA circuit system of the virtual signals from thermal motion simulations in optical tweezers

Optically trapped nanospheres are demonstrated capable of atto-Newton force sensing, where its experiment need to control the modulation voltages of the laser power according to the positions of the trapped nanosphere in high speed. In this paper, position fluctuations of the trapping nanospheres due to thermal motions are simulated using Monte-Carlo method and finite difference method. Equal-scale amplified transformations of those position sequences are generated as the discrete voltage signal of the virtual position detector. A high-speed digital incremental PID(Proportion-Integration-Differentiation) control system is developed by a low-cost FPGA circuit system, which can generate feedback voltage signals correspondingly. The responsive signal frequency is up to 1MHz with a time delay of 0.3μs and quite high amplitude stability. It is validated to integrate the virtual position detector and the PID feedback system into a low-cost semi-physical system, which can test various feedback cooling mechanisms for the complex systems of optical tweezers in vacuum. It will be a further step relative to the pure simulations in digital computers and provide references for the development of optical tweezers in vacuum.

FPGAD efender

Sharing configuration bitstreams rather than netlists is a very desirable feature to protect IP or to share IP without longer CAD tool processing times. Furthermore, an increasing number of systems could hugely benefit from serving multiple users on the same FPGA, for example, for resource pooling in cloud infrastructures. This article researches the threat that a malicious application can impose on an FPGA-based system in a multi-tenancy scenario from a hardware security point of view. In particular, this article evaluates the risk systematically for FPGA power-hammering through short-circuits and self-oscillating circuits, which potentially may cause harm to a system. This risk includes implementing, tuning, and evaluating all FPGA self-oscillators known from the literature but also developing a large number of new power-hammering designs that have not been considered before. Our experiments demonstrate that malicious circuits can be tuned to the point that just 3% of the logic available on an Ultra96 FPGA board can draw the power budget of the entire FPGA board. This fact suggests a waste power potential for datacenter FPGAs in the range of kilowatts. In addition to carefully analyzing FPGA hardware security threats, we present the FPGA virus scanner FPGAD efender , which can detect (possibly) any self-oscillating FPGA circuit, as well as detecting short-circuits, high fanout nets, and a tapping onto signals outside the scope of a module for protecting data center FPGAs, such as Xilinx UltraScale+ devices at the bitstream level.

Improved error detection performance of logic implication checking in FPGA circuits

Increased feature scaling to achieve high performance of miniaturized circuits has increased concerns related to their reliability as smaller circuits age faster. This means that more computational errors due to defects are expected in modern nanoscale circuits. Logic implication checking is a concurrent error detection technique that can detect a partial number of these errors at reduced hardware costs. However, implications-based error detection suffers from a low error coverage in FPGA-implemented circuits making it useless for any practical purposes. In this paper, we identify the reasons for a degraded performance of implication checking in FPGAs and propose multi-wire implications towards achieving better error detection probabilities (Pdetection). The addition of multi-wire implications boosts the number of candidate implications and contributes more valuable implications thereby increasing the average Pdetection achieved by almost 1.7 times at around 65.7% with only a 25% increase in the average area overhead for the given test circuits. Moreover, we show that the efficiency of implications in detecting errors not only varies from one circuit to another but that it also depends largely on the specific implementation of the circuit under test as supported through analytic analyses and comparisons between experimental results obtained from hardware fault injection of the implemented circuits and fault simulations on corresponding circuit netlists.

Secure Hybrid Crypto-system AES/RSA on FPGA for Data Communication

With the development of information technologies, our environment is surrounded by digital data that transit via networks. When data are important, they become vulnerable to external attacks which can be avoided by using cryptography which provides confidentiality, integrity and availability required to secure digital data transactions such as e- commerce, mobile telephony and Internet. This paper deals with securing data transmitted over a network composed by a server and several clients, where a security platform has been integrated into the server and embedded on an FPGA circuit. The protection of data transfer between clients is provided by hybrid cryptography combining symmetric and asymmetric cryptographies. The security of client-server communication is ensured by the AES protocol and the Diffie-Hellman key exchange protocol. To offer a good management of keys and their sharing, a dedicated system for generating keys is designed to fit with public key infrastructures. This system is a part of the server and has been implemented using JAVA language and executed on a computer. This communication system provides a Graphical User Interface (GUI) offering to clients ease and flexibility in transferring their data.

FPGA implementation of a wireless sensor node with a built-in ADALINE neural network coprocessor for vibration analysis and fault diagnosis in machine condition monitoring

Abstract Industry is a very attractive research field for wireless sensor network (WSN) applications. This is demonstrated by the creation of a special category of these networks dedicated to industrial applications, called industrial wireless sensor networks (IWSN). The sensor node, the main component of the network, must have several characteristics, such as a very high processing speed, reliable results, communication capabilities, and reduced transmission time. In this article, we outline the results of replacing the fast Fourier transform (FFT) processing of vibrational signals with an artificial adaptive linear element (ADALINE) neural network in order to extract the harmonics of the signals and thus detect faults in rotating machines. In addition, a MicroBlaze soft-core processor and an nRF24L01+ transmitter was chosen to manage various tasks within the node and the data exchange between the nodes of the network. A Digilent Cmod A7 platform with an Artix-7 FPGA circuit from Xilinx was selected to implement the different blocks that constitute the wireless node. Practical tests showed that the choice of the ADALINE enabled us to achieve the desired results by reducing the processing time to 7.478 ms, which is a reduction of time of approximately 85% compared to results obtained in scientific research. In addition, we have reduced the number of transmitted packets to only two. These results will have a positive impact on the performance of the node, with measurements using a periodic measurement methodology showing that the lifetime of the node can reach up to 17 h.

Grayscale image formats for edge detection and for its FPGA implementation

The aim of this paper is analysis of image formats used for FPGA implementation of edge detection methods. All cameras used in FPGA applications give Raw RGB output video format, some cameras provide also YUV, YCbCr, RGB565/555 or compressed JPEG formats. If the FPGA circuit has limited number of configurable logic blocks (CLB) the JPEG format seems to be good solution how to increase the size of the processed image. On the other hand, using an image with lossy compression can more or less affect the overall result of image processing. The first goal of this paper is to show whether lossy image compression can affect the quality of edge detection. The results presented in this article show that lossy image compression can impair the efficiency of edge detection by up to six percent. Many researchers have proposed FPGA implementation of some edge detection methods. Usually their first step is RGB to grayscale conversion because they use edge detection methods for grayscale images. The second goal of this paper is to show that a performance of FPGA implementation can be improved if YUV, YCbCr or Raw RGB camera output formats are used instead of RGB format.

SEE Fault Sensitivity Analysis and Security Reinforcement Design for FPGA Circuits Based on Complex Network

There may exist many high-energy particles in spacecraft, so the FPGA circuits design needs corresponding sensitivity analysis and security reinforcement of anti-SEE (Single-event effects). However, it may be impractical to perform such measures to all modules of FGPA circuits due to limited resources. To identify the key modules which have a vital impact on the design and operation of FPGA circuits in spacecraft, this paper presents a novel scheme based on complex network for modeling the modules considering both the circuit functional structure and signal interaction relationship between modules. First, complex networks like MSN (Module Structure Network) and SFN (Signal Flow Network) are established to identify modules by treating each module as a node, and indicators including degree centrality (DC), betweenness centrality (BC), clustering coefficient (CC), etc., are calculated. Then, an entropy-weight method (EWM) is utilized to calculate the indicators comprehensively for identifying key modules. Next, network efficiency and sensitivity analysis are performed for failure modes. Finally, a case study is carried out, demonstrating the effectiveness of the proposed scheme for the key module identification. This work provides useful technical support for engineers in spacecraft FPGA circuits design and performance enhancement.

FPGA design and circuit implementation of a new four-dimensional multistable hyperchaotic system with coexisting attractors

This research work focuses upon the FPGA design and electronic circuit implementation of a new multistable four-dimensional hyperchaotic system. This work starts with the dynamics and phase plots of a new four-dimensional hyperchaos system. A detailed bifurcation analysis is carried out for the new hyperchaos system, and special properties such as multistability with coexisting attractors are reported for the new system. An electronic circuit model using MultiSim of the new hyperchaos system is designed. Finally, an FPGA-based design of the new hyperchaos system is performed by applying two numerical methods. Circuit simulation and FPGA design of the new hyperchaos system are very useful for practical applications of the new hyperchaos system.

FPGA design and circuit implementation of a new four-dimensional multistable hyperchaotic system with coexisting attractors

FPGA design and circuit implementation of a new four-dimensional multistable hyperchaotic system with coexisting attractors

A Lightweight Wireless Overpressure Node based Efficient Monitoring for Shock Waves

Overpressure measurement is an important approach to evaluate the power of shock wave (SW) monitoring. Traditional wired monitoring systems exhibit the limitations of high-cost, heavyweight, troublesome maintenance, and big-data transmission in SW monitoring. In this article, a new lightweight FPGA-based wireless overpressure node (LFWON) with the resistance to high-temperature and high-pressure environment for SW monitoring. The proposed LFWON is based on the Spartan-6 XC6SLX9-2TQG144C FPGA circuit, via a serial peripheral interface to the RF transceiver and data bus to the NAND flash chip for data management. To validate the LFWON, experimental tests in terms of dynamic parameters and network quality are performed in a real blast testing with 8-kg trinitrotoluene. This article is conducted to provide new insights into how the antishocking structure and sensing algorithm of wireless sensor node is designed in SW monitoring for acquiring overpressure accurately. The results show that the errors of $\Delta P$ (7 ${\text{m}}$ −12 ${\text{m}}$ ), ${t_d}$ (>6 ${\text{m}}$ ), and ${I^ + }$ (3 ${\text{m}}$ −24 ${\text{m}}$ ) from proposed LFWON are below 20% in comparison with wired system. In addition, the RSSI value of LFWON should be set above −70 ${\text{dBm}}$ for stable communication quality.

Correction to “SEE Fault Sensitivity Analysis and Security Reinforcement Design for FPGA Circuits Based on Complex Network”

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Qunatum-Dot Cellular Automata Technology based Optimized Multiplexers Design

Multiplexer plays a dynamic role in the optimization of a digital circuit (FPGA, ALU and memory circuits etc) implementations. Due to continuous Scaling of CMOS device, has already reached to the minimum transistor size, hence , it is not possible to reduce the transistor dimensions further without scaling issues and functionality affect. QCA is one of the emerging and promising new nanotechnologies and is suitable to replace conventional CMOS technology, and potentially able to solve the physical limitations and challenges of CMOS scaling issues. In this paper, the proposed 2:1 multiplexer structure makes the use of inherent characteristics of QCA cells to act as an efficient multiplexer. The proposed QCA based multiplexer architecture improves 50% of design area, 29% of cell count and 75% of the cost when compared with the earlier designed best multiplexer architectures. Higher order multiplexers 4:1 and 8:1 are also designed using proposed 2:1 multiplexer which improved performance to a greater extent relative to existing efficient multiplexer architectures. The design and simulation of circuits have been performed using software tool QCA Designer Version 2.0.3.

Two-dimensional position-sensitive spectrometer for registration of ionizing radiation

A new two-coordinate position-sensitive spectrometer for the measurements of spatial and energy distribution of ionizing particles was developed. The sensitive elements of the device are two orthogonal 64 strip semiconductor detectors whose signals are read out by two Application-Specific Integrated Circuits (ASIC) IDE1140 comprising 64 spectrometric channels each. Control, pre-processing data acquisition and transfer to a computer are carried out using FPGA circuit EP3C16Q240. The main spectrometer characteristics obtained in the measurements are: equivalent noise charge of 0.7 fC and integral nonlinearity is below 1% in the range from 5 to 160 fC.

I can't believe it's not (only) software!

There is a steady increase in the size of data stored and processed as part of data science applications, leading to bottlenecks and inefficiencies at various layers of the stack. One way of reducing such bottlenecks and increasing energy efficiency is by tailoring the underlying distributed storage solution to the application domain, using resources more efficiently. We explore this idea in the context of a popular column-oriented storage format used in big data workloads, namely Apache Parquet. Our prototype uses an FPGA-based storage node that offers high bandwidth data deduplication and a companion software library that exposes an API for Parquet file access. This way the storage node remains general purpose and could be shared by applications from different domains, while, at the same time, benefiting from deduplication well suited to Apache Parquet files and from selective reads of columns in the file. In this demonstration we show, on the one hand, that by relying on the FPGA's dataflow processing model, it is possible to implement in-line deduplication without increasing latencies significantly or reducing throughput. On the other hand, we highlight the benefits of implementing the application-specific aspects in a software library instead of FPGA circuits and how this enables, for instance, regular data science frameworks running in Python to access the data on the storage node and to offload filtering operations.