Abstract
FPGA has recently played an increasingly important role in heterogeneous computing, but Register Transfer Level design flows are not only inefficient in design, but also require designers to be familiar with the circuit architecture. High-level synthesis (HLS) allows developers to design FPGA circuits more efficiently with a more familiar programming language, a higher level of abstraction, and automatic adaptation of timing constraints. When using HLS tools, such as Xilinx Vivado HLS, specific design patterns and techniques are required in order to create high-performance circuits. Moreover, designing efficient concurrency and data flow structures requires a deep understanding of the hardware, imposing more learning costs on programmers. In this paper, we propose a set of functional patterns libraries based on the MapReduce model, implemented by C++ templates, which can quickly implement high-performance parallel pipelined computing models on FPGA with specified simple parameters. The usage of this pattern library allows flexible adaptation of parallel and flow structures in algorithms, which greatly improves the coding efficiency. The contributions of this paper are as follows. (1) Four standard functional operators suitable for hardware parallel computing are defined. (2) Functional concurrent programming patterns are described based on C++ templates and Xilinx HLS. (3) The efficiency of this programming paradigm is verified with two algorithms with different complexity.
Highlights
Introduction published maps and institutional affilFPGA is widely used and has rapidly developed in high-performance computing, due to its parallel execution, high computational performance, low power consumption, and short development cycle compared to Application Specific Integrated Circuit (ASIC).with the increasing Scale of system-on-a-chip, the user designing process becomes more and more complex, and the drawbacks of traditional Register Transfer Level (RTL) approaches become prominent
We propose high-performance computing pattern using template-based hardware generation strategy through extending C++-based Xilinx Vivado High-level synthesis (HLS) tools
We evaluate our work in two algorithms: the vector distances algorithm and the Quantum-behaved Particle Swarm Optimization (QPSO) algorithm
Summary
Lan Huang 1,2,‡ , Teng Gao 1,‡ , Dalin Li 1,† , Zihao Wang 1 and Kangping Wang 1,2, *. Key Laboratory of Symbolic Computation and Knowledge Engineering, Jilin University, Changchun 130012, China. Current address: Zhuhai Laboratory of Key Laboratory of Symbol Computation and Knowledge Engineering of Ministry of Education, Department of Computer Science and Technology, Zhuhai College of Jilin.
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