FPGA-based Implementation Research Articles

A New 5-D Multistable Hyperchaotic System With Three Positive Lyapunov Exponents: Bifurcation Analysis, Circuit Design, FPGA Realization and Image Encryption

In this work, we describe the model of a new 5-D hyperchaotic system with three positive Lyapunov exponents. Since the maximum positive Lyapunov exponent of the proposed hyperchaotic system is larger than twelve, the new hyperchaotic system is highly hyperchaotic. We also show that the new 5-D hyperchaotic system exhibits multistability with coexisting attractors. Using Multisim, we design an electronic circuit for the new 5-D hyperchaotic system. The hardware implementation of the new 5-D hyperchaotic system is done by applying two numerical methods. From the experimental results of the FPGA-based implementation, we show that the attractors observed in a Lecroy oscilloscope are in good agreement with numerical simulations. To prove the reliability of the proposed system for cybersecurity purposes, we presented a new image cryptosystem using our hyperchaotic system. Experimental outcomes show the efficiency and the reliability of our cryptosystem based on the proposed hyperchaotic system.

FPGA-Based Implementation of a CNN Architecture for the On-Board Processing of Very High-Resolution Remote Sensing Images

Over the last years, Convolutional Neural Networks (CNNs) have been widely used in remote sensing applications, such as marine surveillance, traffic management or road networks detection. However, since CNNs have extremely high computation, bandwith and memory requirements, the hardware implementation of a CNN on space-grade devices like FPGAs for the on-board processing of the acquired images has brought many challenges. In fact, FPGAs show great advantages in terms of reconfigurability and performance-power ratio, whichmakes them a suitable election to deploy CNNs, although the computational capabilities of this type of hardware devices available on-board is limited, so implementations have to be carefully planned. In this paper, the authors present their work towards the implementation of an efficient CNN onto a spacegrade FPGA in order to achieve the on-board processing of very-high resolution remotely sensed images as soon as the data are provided by the sensor. All this work has been conducted within the EU-funded VIDEO project. As it will be presented in this paper, the work includes the introduction of a methodology based on the project constraints, the evaluation of different state-of-the-art CNN architectures by means of a new efficiency measurement also proposed in this work, the introduction of a new efficient CNN architecture, and finally, its optimized hardware implementation by means of high-level synthesis tools.

Stochastic Computing Emulation of Memristor Cellular Nonlinear Networks.

Cellular Nonlinear Networks (CNN) are a concept introduced in 1988 by Leon Chua and Lin Yang as a bio-inspired architecture capable of massively parallel computation. Since then, CNN have been enhanced by incorporating designs that incorporate memristors to profit from their processing and memory capabilities. In addition, Stochastic Computing (SC) can be used to optimize the quantity of required processing elements; thus it provides a lightweight approximate computing framework, quite accurate and effective, however. In this work, we propose utilization of SC in designing and implementing a memristor-based CNN. As a proof of the proposed concept, an example of application is presented. This application combines Matlab and a FPGA in order to create the CNN. The implemented CNN was then used to perform three different real-time applications on a 512 × 512 gray-scale and a 768 × 512 color image: storage of the image, edge detection, and image sharpening. It has to be pointed out that the same CNN was used for the three different tasks, with the sole change of some programmable parameters. Results show an excellent capability with significant accompanying advantages, such as the low number of needed elements further allowing for a low cost FPGA-based system implementation, something confirming the system’s capacity for real time operation.

Design and FPGA based Implementation of IEEE 1588 Precision Time Protocol for Synchronisation in Distributed IoT Applications

ABSTRACT In distributed network applications such as the Internet of Things (IoT), a master clock is used to provide a frame of reference among all constituent nodes. Any drift in the clock on a single node can cause serious cascading effects in a system that largely involves ordered events and time-critical tasks. To provide a stable reference clock, time synchronisation protocols are utilised in distributed systems where client nodes can synchronise their clock with a master node. IEEE 1588 Precision Time Protocol (PTP) is increasingly being used to provide high time synchronisation accuracy in comparison with other synchronisation protocols. In this paper, we have proposed a hardware design and FPGA-based implementation of the IEEE 1588 protocol to be used in wired LAN communication. Experimental results show synchronisation accuracy in the range of few nanoseconds, which is significantly better than the existing implementations. The FPGA implementation was carried out on a Xilinx Artix-7 evaluation board.

An FPGA-Based LOCO-ANS Implementation for Lossless and Near-Lossless Image Compression Using High-Level Synthesis

In this work, we present and evaluate a hardware architecture for the LOCO-ANS (Low Complexity Lossless Compression with Asymmetric Numeral Systems) lossless and near-lossless image compressor, which is based on JPEG-LS standard. The design is implemented in two FPGA generations, evaluating its performance for different codec configurations. The tests show that the design is capable of up to 40.5 MPixels/s and 124 MPixels/s per lane for Zynq 7020 and UltraScale+ FPGAs, respectively. Compared to the single thread LOCO-ANS software implementation running in a 1.2 GHz Raspberry Pi 3B, each hardware lane achieves 6.5 times higher throughput, even when implemented in an older and cost-optimized chip like the Zynq 7020. Results are also presented for a lossless only version, which achieves a lower footprint and approximately 50% higher performance than the version that supports both lossless and near-lossless. Interestingly, these great results were obtained applying High-Level Synthesis, describing the coder with C++ code, which tends to establish a trade-off between design time and quality of results. These results show that the algorithm is very suitable for hardware implementation. Moreover, the implemented system is faster and achieves higher compression than the best previously available near-lossless JPEG-LS hardware implementation.

When Massive GPU Parallelism Ain’t Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network

Multidimensional Long Short-Term Memory (MD-LSTM) neural network is an extension of one-dimensional LSTM for data with more than one dimension. MD-LSTM achieves state-of-the-art results in various applications, including handwritten text recognition, medical imaging, and many more. However, its implementation suffers from the inherently sequential execution that tremendously slows down both training and inference compared to other neural networks. The main goal of the current research is to provide acceleration for inference of MD-LSTM. We advocate that Field-Programmable Gate Array (FPGA) is an alternative platform for deep learning that can offer a solution when the massive parallelism of GPUs does not provide the necessary performance required by the application. In this article, we present the first hardware architecture for MD-LSTM. We conduct a systematic exploration to analyze a tradeoff between precision and accuracy. We use a challenging dataset for semantic segmentation, namely historical document image binarization from the DIBCO 2017 contest and a well-known MNIST dataset for handwritten digit recognition. Based on our new architecture, we implement FPGA-based accelerators that outperform Nvidia Geforce RTX 2080 Ti with respect to throughput by up to 9.9 and Nvidia Jetson AGX Xavier with respect to energy efficiency by up to 48 . Our accelerators achieve higher throughput, energy efficiency, and resource efficiency than FPGA-based implementations of convolutional neural networks (CNNs) for semantic segmentation tasks. For the handwritten digit recognition task, our FPGA implementations provide higher accuracy and can be considered as a solution when accuracy is a priority. Furthermore, they outperform earlier FPGA implementations of one-dimensional LSTMs with respect to throughput, energy efficiency, and resource efficiency.

An Efficient FPGA-Based Convolutional Neural Network for Classification: Ad-MobileNet

Convolutional Neural Networks (CNN) continue to dominate research in the area of hardware acceleration using Field Programmable Gate Arrays (FPGA), proving its effectiveness in a variety of computer vision applications such as object segmentation, image classification, face detection, and traffic signs recognition, among others. However, there are numerous constraints for deploying CNNs on FPGA, including limited on-chip memory, CNN size, and configuration parameters. This paper introduces Ad-MobileNet, an advanced CNN model inspired by the baseline MobileNet model. The proposed model uses an Ad-depth engine, which is an improved version of the depth-wise separable convolution unit. Moreover, we propose an FPGA-based implementation model that supports the Mish, TanhExp, and ReLU activation functions. The experimental results using the CIFAR-10 dataset show that our Ad-MobileNet has a classification accuracy of 88.76% while requiring little computational hardware resources. Compared to state-of-the-art methods, our proposed method has a fairly high recognition rate while using fewer computational hardware resources. Indeed, the proposed model helps to reduce hardware resources by more than 41% compared to that of the baseline model.

FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

In this paper, we propose a range-Doppler algorithm (RDA)-based synthetic aperture radar (SAR) processor for real-time SAR imaging and present FPGA-based implementation results. The processing steps for the RDA include range compression, range cell migration correction (RCMC), and azimuth compression. A matched filtering unit (MFU) and an RCMC processing unit (RPU) are required for real-time processing. Therefore, the proposed RDA-based SAR processor contains an MFU that uses the mixed-radix multi-path delay commutator (MRMDC) FFT and an RPU. The MFU reduces the memory requirements by applying a decimation-in-frequency (DIF) FFT and decimation-in-time (DIT) IFFT. The RPU provides a variable tap size and variable interpolation kernel. In addition, the MFU and RPU are designed to enable parallel processing of four 32-bit which are transferred via a 128-bit AXI bus. The proposed RDA-based SAR processor was designed using Verilog-HDL and implemented in a Xilinx UltraScale+ MPSoC FPGA device. After comparing the execution time taken by the proposed SAR processor with that taken by an ARM cortex-A53 microprocessor, we observed a 85-fold speedup for a 2048 × 2048 pixel image. A performance evaluation based on related studies indicated that the proposed processor achieved an execution time that was approximately 6.5 times less than those of previous FPGA implementations of RDA processors.

FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review

The field programmable gate array (FPGA) devices are ideal solutions for high-speed processing applications, given their flexibility, parallel processing capability, and power efficiency. In this review paper, at first, an overview of the key applications of FPGA-based platforms in 5G networks/systems is presented, exploiting the improved performances offered by such devices. FPGA-based implementations of cloud radio access network (C-RAN) accelerators, network function virtualization (NFV)-based network slicers, cognitive radio systems, and multiple input multiple output (MIMO) channel characterizers are the main considered applications that can benefit from the high processing rate, power efficiency and flexibility of FPGAs. Furthermore, the implementations of encryption/decryption algorithms by employing the Xilinx Zynq Ultrascale+MPSoC ZCU102 FPGA platform are discussed, and then we introduce our high-speed and lightweight implementation of the well-known AES-128 algorithm, developed on the same FPGA platform, and comparing it with similar solutions already published in the literature. The comparison results indicate that our AES-128 implementation enables efficient hardware usage for a given data-rate (up to 28.16 Gbit/s), resulting in higher efficiency (8.64 Mbps/slice) than other considered solutions. Finally, the applications of the ZCU102 platform for high-speed processing are explored, such as image and signal processing, visual recognition, and hardware resource management.

FPGA-Based Implementation of an Optimization Algorithm to Maximize the Productivity of a Microbial Electrolysis Cell

In this work, the design of the hardware architecture to implement an algorithm for optimizing the Hydrogen Productivity Rate (HPR) in a Microbial Electrolysis Cell (MEC) is presented. The HPR in the MEC is maximized by the golden section search algorithm in conjunction with a super-twisting controller. The development of the digital architecture in the implementation step of the optimization algorithm was developed in the Very High Description Language (VHDL) and synthesized in a Field Programmable Gate Array (FPGA). Numerical simulations demonstrated the feasibility of the proposed optimization strategy embedded in an FPGA Cyclone II. Results showed that only 21% of the total logic elements, 5.19% of dedicated logic registers, and 64% of the total eight-bits multipliers of the FPGA were used. On the other hand, the estimated power consumption required by the FPGA-embedded optimization algorithm was only 146 mW.

An FPGA-based architecture for a latitude and longitude correction in autonomous navigation tasks

The response speed of the intelligent systems embedded in an autonomous vehicle is crucial for its correct operation and reduction of the risks on the road derived from autonomous driving. For that reason, it is necessary to optimize the algorithms that process the data from the sensors; with that aim the Field-Programmable Gate Arrays (FPGAs) offer the possibility of parallelizing the tasks to be carried out by mentioned systems, accelerating their response and improving their performance. In this regard, this paper introduces a fuzzy absolute position correction system, which corrects the latitude and longitude data registered from a GPS Pmod sensor and its implementation on a FPGA to speed up the correction results. A necessary comparison of the algorithm execution time on different platforms such as: A Raspberry pi 4 model B, a personal computer (PC) with Ubuntu 18.04.4 64-bit and the FPGA model, was performed to validate the results and the effectiveness of the implementation. The correction system was validated in software and hardware on 4 different routes, each of them with a large number of samples. The results were highly similar in the three platforms; however, the FPGA-based implementation offers a speed up of 40000x compared to software-based implementations.

A New 4D Piecewise Linear Multiscroll Chaotic System with Multistability and Its FPGA-Based Implementation

Due to the complex behavior of a multiscroll chaotic system, it is a good candidate for the secure communications. In this paper, by adding an additional variable to the modified Lorenz-type system, a new chaotic system that includes only linear and piecewise items but can generate 4n + 4 scroll chaotic attractors via choosing the various values of natural number n is proposed. Its dynamics including bifurcation, multistability, and symmetric coexisting attractors, as well as various chaotic and periodic behaviors, are analyzed by means of attraction basin, bifurcation diagram, dynamic map, phase portrait, Lyapunov exponent spectrum, and C0 complexity in detail. The mechanism of the occurrence for generating multiscroll chaotic attractors is presented. Finally, this multiscroll chaotic system is implemented by using the Altera Cyclone IV EP4CE10F17C8 FPGA. It is found that this FPGA-based design has an advantage of requiring less resources for 0% of the embedded multipliers and 0% of the PLLs of this FPGA are occupied.

Low-Delay FPGA-Based Implementation of Finite Field Multipliers

Arithmetic operations over binary extension fields GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) have many important applications in domains such as cryptography, code theory and digital signal processing. These applications must be fast, so low-delay implementations of arithmetic circuits are required. Among GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) arithmetic operations, field multiplication is considered the most important one. For hardware implementation of multiplication over binary finite fields, irreducible trinomials and pentanomials are normally used. In this brief, low-delay FPGA-based implementations of bit-parallel GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) polynomial basis multipliers are presented, where a new multiplier based on irreducible trinomials is given. Several post-place and route implementation results in Xilinx Artix-7 FPGA for different GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) finite fields are reported. Experimental results show that the proposed multiplier exhibits the best delay, with a delay improvement of up to 4.7%, and the second best Area×Time complexities when compared with similar multipliers found in the literature.

A real-time FPGA-based implementation for detection and sorting of bio-signals

Extracting and analyzing relevant information from bio-signal recordings are complex tasks in which action potential detection and sorting processes take place, moreover if these are performed in real time. In this regard, the present paper introduces real-time FPGA-based architectures for detection and sorting of bio-signals, in particular macaque and human pancreatic signals. Action potential detection is performed by using an adaptive threshold. Also, during this process we have identified six different action potential shapes from the signals, which have been used to classify the action potentials. Our implementation runs at a frequency of 100 MHz with a low resource consumption for both architectures, and action potentials can be also observed in real time during a simulation in an OLED display.

Real-time FPGA-based implementation of the AKAZE algorithm with nonlinear scale space generation using image partitioning

The first step in a scale invariant image matching system is scale space generation. Nonlinear scale space generation algorithms such as AKAZE, reduce noise and distortion in different scales while retaining the borders and key-points of the image. An FPGA-based hardware architecture for AKAZE nonlinear scale space generation is proposed to speed up this algorithm for real-time applications. The three contributions of this work are (1) mapping the two passes of the AKAZE algorithm onto a hardware architecture that realizes parallel processing of multiple sections, (2) multi-scale line buffers which can be used for different scales, and (3) a time-sharing mechanism in the memory management unit to process multiple sections of the image in parallel. We propose a time-sharing mechanism for memory management to prevent artifacts as a result of separating the process of image partitioning. We also use approximations in the algorithm to make hardware implementation more efficient while maintaining the repeatability of the detection. A frame rate of 304 frames per second for a 1280 times 768 image resolution is achieved which is favorably faster in comparison with other work.

Area-Time Efficient Hardware Architecture for Signature Based on Ed448

In this brief, we proposed a highly-optimized FPGA-based implementation of the Ed448 digital signature algorithm. Despite significant progress in elliptic curve cryptography (ECC) implementations, Ed448 hardware architecture, to the best of our knowledge, has not been investigated in the literature. In this work, we demonstrate a high throughput while maintaining low resource architecture for Ed448 by employing a new combined algorithm for refined Karatsuba-based multiplier with precise scheduling. Furthermore, a compact distributed memory unit is developed to increase speed while keeping the area low. Our variable-base-point Ed448 architecture performs 327 signatures and 189 verifications per second at a notably higher security level of 224 bits, using not more than 6,617 Slices and 16 DSPs on a Xilinx Artix-7 FPGA. We also proposed possible countermeasures and extensions to Ed448 to counter the physical attacks.

FPGA-based implementation of two-step schedulers for modular optical interconnection networks

Optical interconnection networks promise to overcome the limitations of current electronic switching fabrics, enabling higher throughput, lower latency, and lower power consumption. Multi-plane architectures, based on multiple optical switching domains (e.g., space, time, wavelength, orbital angular momentum), are gaining research attention because of their modularity and scalability compared to single-domain switches. An effective scheduler, namely, the two-step scheduler (TSS), has been proposed for multi-plane optical interconnection networks, exploiting their modularity to speed up computations while satisfying the peculiar scheduling constraints. In this paper, a hardware implementation of TSS for modular optical interconnection networks is presented and thoroughly assessed. Both scheduling steps are parallelized with the aim of optimizing the execution time. iSLIP and longest queue first (LQF) scheduling algorithms are exploited in each step, resulting in four TSS configurations that are compared among each other and with classical single-step schedulers (SSSs) in terms of scheduling and hardware performance. TSS outperforms SSS in terms of the number of iterations, maximum operating frequency, worst-case scheduling duration, and required logic resources (i.e., scalability) at the expense of a slight latency penalty. Among all TSS configurations, LQF-based TSS guarantees the lowest scheduling latency, while iSLIP-based TSS minimizes the scheduling duration and the use of field programmable gate array (FPGA) resources.

Step-by-Step Development and Implementation of FS-MPC for a FPGA-Based PMSM Drive System

In this paper, finite-set model-predictive control (FS-MPC) is inducted for a motor drive system. The dynamic response and multiple constraint handling nature of FS-MPC are the major factors that stand out among the controller family. However, for real-time implementation, the computational burden of FS-MPC is a primary concern. Due to the parallel processing nature and discrete nature of the hardware platform, the field-programmable gate array (FPGA) can be an alternative solution for the real-time implementation of the controller algorithm. The FPGA is capable of handling the computational requirements for FS-MPC implementation; however, the system development involves multiple steps that lead to a time-consuming debugging process. Moreover, specific hardware coding skill makes it more complex, corresponding to an increase in system complexity, which leads to a tedious task for the system development. This paper presents a FPGA-based implementation of the predictive current control of a permanent magnet synchronous motor (PMSM). FS-MPC of the PMSM drive system is designed and implemented using the digital model integration approach provided by the Xilinx system generator (XSG) and VIVADO platform. The step change in the load disturbance as well as the reference speed is considered for the analysis of the controller for the motor drive system. Moreover, the steady state error and harmonic distortion in the motor current is considered for an in-depth analysis of the system performance corresponding to different sampling frequencies.

A compact FPGA-based montgomery modular multiplier

&lt;span&gt;This paper presents the FPGA-based implementation of compact montgomery modular multiplier (MMM). MMM serves as a building block commonly required in security protocols relying on public key encryption. The proposed design is intended for hardware applications of lightweight cryptographic modules that is utilized for the system on chip (SoC) and internet of things (IoT) devices. The proposed design is a modification in the structure of MMM without any multiplication or subtraction processes. The main target of the new modification is enhancing the performance and reducing the area of the MMM hardware module. The operands and internal variables of the proposed hardware circuit is optimized to be bounded to the smallest efficient size to minimize the area and the critical path delay. The proposed design was coded in VHDL, implemented in the Virtex-6 FPGA, and its performance was analyzed utilizing XILINX ISE tools. Our design occupies the smallest area comparing with other implementations on the same FPGA type. The proposed design saves in a range between 60.0 and 99.0% of the resources compared with other relevant designs.&lt;/span&gt;

The Design and FPGA-Based Implementation of a Stream Cipher Based on a Secure Chaotic Generator

In this study, with an FPGA-board using VHDL, we designed a secure chaos-based stream cipher (SCbSC), and we evaluated its hardware implementation performance in terms of computational complexity and its security. The fundamental element of the system is the proposed secure pseudo-chaotic number generator (SPCNG). The architecture of the proposed SPCNG includes three first-order recursive filters, each containing a discrete chaotic map and a mixing technique using an internal pseudo-random number (PRN). The three discrete chaotic maps, namely, the 3D Chebyshev map (3D Ch), the 1D logistic map (L), and the 1D skew-tent map (S), are weakly coupled by a predefined coupling matrix M. The mixing technique combined with the weak coupling technique of the three chaotic maps allows preserving the system against side-channel attacks (SCAs). The proposed system was implemented on a Xilinx XC7Z020 PYNQ-Z2 FPGA platform. Logic resources, throughput, and cryptanalytic and statistical tests showed a good tradeoff between efficiency and security. Thus, the proposed SCbSC can be used as a secure stream cipher.