Abstract
In this paper, finite-set model-predictive control (FS-MPC) is inducted for a motor drive system. The dynamic response and multiple constraint handling nature of FS-MPC are the major factors that stand out among the controller family. However, for real-time implementation, the computational burden of FS-MPC is a primary concern. Due to the parallel processing nature and discrete nature of the hardware platform, the field-programmable gate array (FPGA) can be an alternative solution for the real-time implementation of the controller algorithm. The FPGA is capable of handling the computational requirements for FS-MPC implementation; however, the system development involves multiple steps that lead to a time-consuming debugging process. Moreover, specific hardware coding skill makes it more complex, corresponding to an increase in system complexity, which leads to a tedious task for the system development. This paper presents a FPGA-based implementation of the predictive current control of a permanent magnet synchronous motor (PMSM). FS-MPC of the PMSM drive system is designed and implemented using the digital model integration approach provided by the Xilinx system generator (XSG) and VIVADO platform. The step change in the load disturbance as well as the reference speed is considered for the analysis of the controller for the motor drive system. Moreover, the steady state error and harmonic distortion in the motor current is considered for an in-depth analysis of the system performance corresponding to different sampling frequencies.
Highlights
Permanent magnet synchronous motors (PMSMs) have been used in high-performanceAC motor drives in industrial as well as domestic applications due to the advantages of high efficiency, a high torque-to-weight ratio and a wide range of speed operations [1,2,3]
This paper presents the design and development of finite-set model-predictive control (FS-Model predictive control (MPC)) for a PMSM drive system that can be utilized in real-time field-programmable gate array (FPGA) implementations
Where id∗ and iq∗ are the reference stator current on the d- and q-axes, respectively, idj (k + 1) and iqj (k + 1) are the predicted current corresponding to the inverter voltage vector and j represents the number of predicted currents, according to the number of possible switching states. id* is considered to be zero in the case of the surface permanent magnet synchronous motor (SPMSM)
Summary
AC motor drives in industrial as well as domestic applications due to the advantages of high efficiency, a high torque-to-weight ratio and a wide range of speed operations [1,2,3]. In [18], a total harmonic distortion (THD)-oriented FCS-MPC controller is designed for single-phase inverters To achieve this goal, a modified cost function is constructed using a linear combination, with weight factors of the current fundamental tracking error and an instantaneous THD value. This paper presents the design and development of FS-MPC for a PMSM drive system that can be utilized in real-time FPGA implementations. The FS-MPC algorithm is developed for a three-phase, two-level voltage source inverter (VSI)-fed PMSM drive system using an optimization function in terms of current. The sections of this paper are organized as follows: Section 2 describes the algorithm of FS-MPC for the PMSM drive system considering the discrete-time mathematical model of the motor and three-phase VSI.
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