FPGA-based Implementation Research Articles

A Reduced-Order Digital Twin FPGA-Based Implementation With Self-Awareness Capabilities for Power Electronics Applications

A Reduced-Order Digital Twin FPGA-Based Implementation With Self-Awareness Capabilities for Power Electronics Applications

FPGA-based Implementation of Consistent Flow Configuration System for Software-defined Networking

FPGA-based Implementation of Consistent Flow Configuration System for Software-defined Networking

Modelling, bifurcation analysis, circuit design and FPGA-based implementation of a new chaotic jerk system exhibiting Hopf bifurcations

Modelling, bifurcation analysis, circuit design and FPGA-based implementation of a new chaotic jerk system exhibiting Hopf bifurcations

FPGA-Based Implementation of SCADA System for Fuel Management

With the emergence of Digital Processors and Logic Design technologies, like FPGAs, the trend of using IC-based plug-and-play modules has been minimized. The focus is commercial off-shelf designing and developing modules and sub-modules on new FPGA technology. Some of the critical factors that make FPGA more suitable include enormous computational power, capabilities to perform logic operations, high-speed clocks, fast memory, and various built-in primitives for computation-intensive arithmetic operations. FPGA becomes suitable for implementing data capturing and processing systems with these characteristics. This paper is about designing and developing an FPGA-based Supervisory Control and Data Acquisition (SCADA) System to monitor and control the fuel level transition between two tanks that generally are designed using PLC. PLC-based SCADA systems are easy to implement, but when discussing performance, PLC cannot replace FPGA. The FPGA chosen is Spartan-3 due to its low cost and meeting the industrial temperature needs. At the same time, it may be translated into any advanced FPGA, producing fewer sources and power consumption benefits. The simulator is Xilinx 14.7 ISE, along with SDK. The implemented system provides the inherent amenities of SCADA along with the benefits of high speed, more accuracy, reduced and predictable delay, and a purely digitized system facilitated by the FPGA.

Effect of geometry configuration on bursting oscillations of the mechanical oscillator with strong irrational nonlinearities and its FPGA-based implementation

Effect of geometry configuration on bursting oscillations of the mechanical oscillator with strong irrational nonlinearities and its FPGA-based implementation

Dynamical analysis and synchronization control of flux-controlled memristive chaotic circuits and its FPGA-Based implementation

This paper focuses on addressing the synchronization control problem of memristive chaos through the investigation of a single feedback controller strategy. Our objective is to deploy this strategy on field-programmable gate arrays (FPGA) with the aim of bolstering the security and reliability of memristive chaotic synchronization control. Concurrently, we seek to enhance system performance and fulfill the diverse requirements of various applications. Initially, the study utilizes chaos synchronization theory and the Routh–Hurwitz stability criterion to devise a feedback controller with a single input. This controller plays a crucial role in establishing a synchronization system specifically designed for memristive chaos. Subsequently, the FPGA design approach utilizing DSP Builder is employed to create models for both the single-input feedback controller and the memristive chaotic synchronization control system. This approach facilitates the efficient translation of these theoretical concepts into practical digital circuit implementations. Finally, the paper concludes with an experimental analysis that verifies the feasibility and practical applicability of the FPGA circuit design for memristive chaotic synchronization control.

FPGA implementation of orthogonal hyperchaotic sequences generator based on the CNN: application in multi-user chaotic communications

In this article, we propose an efficient orthogonal hyperchaotic sequences generator for application in multi-user chaotic communication systems. The proposed generator consists of two blocks. The first block generates binary hyperchaotic sequences of varying lengths using a 6-Dimensional Cellular Neural Network (CNN) system, offering a wide range of sequence length choices. The second block uses an optimized selection method to generate multiple sets of orthogonal sequences with interesting correlation properties. The method is based on the balance and correlation properties, where zero cross-correlation between any two sequences is considered. A FPGA-based implementation of the proposed generator is presented. The hardware architecture is designed in VHDL and deployed on a Xilinx Virtex-6 FPGA ML605 evaluation kit. The generator is then analyzed and compared with the existing generator in terms of logic area consumption, throughput, latency, and randomness quality. The comparative analysis results show the effectiveness of the proposed generator, which can achieve a high throughput, low latency, and successfully pass all NIST statistical tests. Moreover, the generated orthogonal hyperchaotic sequences exhibit promising performance in a multi-user Differential Chaos Shift Keying (MU-DCSK) system, outperforming the Walsh-Hadamard sequences in terms of bit-error rate under various channel conditions.

Programmable In-memory Computing Circuit of Fast Hartley Transform

Discrete Hartley transform is a core component of digital signal processing because of its advantages of fast computing speed and less power consumption. Traditional FPGA-based implementation methods have the disadvantage of high latency, which cannot meet the needs of energy-efficient computing in the Internet of Things era. Therefore, A programmable analog memory computing circuit is proposed to accelerate FHT and IFHT calculations for large-scale one-step matrix computation. By adjusting the weight of memristor, different scales of FHT calculation can be achieved. PSPICE simulation results show that the average accuracy of the proposed circuit can reach 99.9%, and the speed can also reach the level of 0.1 μ s. The robustness analysis shows that the circuit can tolerate a certain degree of programming error and resistance tolerance. The designed analog circuit is applied to image compression processing, and the image compression accuracy can reach 99.9%.

FPGA-Based Implementation of an Underwater Quantum Key Distribution System With BB84 Protocol

FPGA-Based Implementation of an Underwater Quantum Key Distribution System With BB84 Protocol

FPGA-Based Implementation of a New 3-D Multistable Chaotic Jerk System with Two Unstable Balance Points

Mechanical jerk systems have applications in several areas, such as oscillators, microcontrollers, circuits, memristors, encryption, etc. This research manuscript reports a new 3-D chaotic jerk system with two unstable balance points. It is shown that the proposed mechanical jerk system exhibits multistability with coexisting chaotic attractors for the same set of system constants but for different initial states. A bifurcation analysis of the proposed mechanical jerk system is presented to highlight the special properties of the system with respect to the variation of system constants. A field-programmable gate array (FPGA) implementation of the proposed mechanical jerk system is given by synthesizing the discrete equations that are obtained by applying one-step numerical methods. The hardware resources are reduced by performing pipeline operations, and, finally, the paper concludes that the experimental results of the proposed mechanical jerk system using FPGA-based design show good agreement with the MATLAB simulations of the same system.

FPGA-Based Implementation of Reverse Electrical Pulse Stress and Measurement system for Gallium Nitride High-Electron-Mobility Transistors

This paper presents a pulse electrical stress and measurement system of GaN high-electron-mobility transistors based on FPGA to apply the electrical stress accurately in the form of square wave pulses and switch to the measuring state in time. The design processes for the FPGA program, software system, and hardware circuit are discussed. The system uses a bipolar isolated gate driver to apply pulses of electrical stress to the gate of GaN HEMTs. The mode switch circuit is used to switch from “stress mode” to “measuring mode” to realize the measuring of electrical parameters of the device under test after stress. The system can achieve electrical pulse stress and assist in analyzing the degradation mechanism of GaN HEMTs.

Efficient hardware mapping of Boolean substitution boxes based on functional decomposition for RFID and ISM band IoT applications

This paper investigates three substitution box (S-box) designs for lightweight ciphers. The proposed designs involve functional decomposition, which is preferable as compared to the look-up tables or logic gates-based S-box designs due to their advantages, as outlined in this paper. The aim is to reduce the number of literals at the input of the S-box to achieve resource reduction in the overall circuit design of the encryption algorithms. The proposed S-box architectures provide optimized resource mapping for specific target hardware, and high throughput along with lesser energy consumption compared to state-of-the-art designs. The proposed S-box designs are applied to the substitution layers of symmetric lightweight block ciphers with a standard security level. In order to be fair in comparison, the overall cipher designs are targeted for similar FPGA-based implementation as used in existing works, while the architectures of the individual 4-bit S-boxes are evaluated using SAED90 nm standard cell libraries. The performance of the proposed S-box designs is observed to be superior at RFID and ISM frequency ranges which can be deployed in applications constrained to low resources as well as demanding high performance and medium security.

TRIM: A Design Space Exploration Model for Deep Neural Networks Inference and Training Accelerators

There is increasing demand for specialized hardware for training deep neural networks, both in edge/IoT environments and in high performance computing systems. The design space of such hardware is very large due to the wide range of processing architectures, deep neural network configurations, and dataflow options. This makes developing deep neural network processors quite complex, especially for training. We present TRIM, an infrastructure to help hardware architects explore the design space of deep neural network accelerators for both inference and training in the early design stages. The model evaluates at the whole network level, considering both inter-layer and intra-layer activities. Given applications, essential hardware specifications, and a design goal, TRIM can quickly explore different hardware design options, select the optimal dataflow and guide new hardware architecture design. We validated TRIM with FPGA-based implementation of deep neural network accelerators and ASIC-based architectures. We also show how to use TRIM to explore the design space through several case studies. TRIM is a powerful tool to help architects evaluate different hardware choices to develop efficient inference and training architecture design. Experimental results show that TRIM is a powerful tool for rapidly exploring the design space of DNN architectures for training and inference.

Real time vision-based implementation of plant disease identification system on FPGA

Plant diseases have turned into a dilemma as it can cause significant reduction in both quality and quantity of agricultural products. To overcome that loss, we implemented a computer vision based real time system that can identify the type of plant diseases. Computer vision-based applications are computationally intensive and time consuming, so FPGA-based implementation is proposed to have a real time identification of plant diseases. In this paper an image processing algorithm is proposed for identifying two types of disease in Potato leaves. The proposed algorithm works well on images taken under different luminance conditions. The hardware/software-based implementation of the proposed algorithm is done on Xilinx ZYNQ SoC FPGA. Results show that our proposed algorithm achieves an accuracy of up to 90%, whereas the hardware implementation takes 0.095 seconds achieving a performance gain of 76.8 times as compared to the software implementation.

FPGA-based implementation of deep neural network using stochastic computing

A serious challenge in artificial real-time applications is the hardware implementation of deep neural networks (DNN). Among various methods, stochastic computing (SC)-based implementations received tremendous attention due to the low hardware overhead. However, the slow convergence rate is a major problem in SC-based neural networks’ implementation, and millions of clock cycles are required to generate a relatively accurate output. The reconfigurability and parallel nature of field programmable gate array (FPGA) chips make them a preferable platform for SC-based DNN implementation. A fully or semi-parallel implementation of DNNs requires extensive hardware resources. In this paper, an efficient method for DNN implementation on an FPGA chip is presented to address these problems. The FPGA chip reconfiguration feature allows a DNN with several different neurons and topologies to be implemented on a single chip. Convergence time is significantly reduced by limiting the length of the stochastic bitstreams and establishing synchronization between the processing units based on precise timing. Furthermore, due to the limited number of input–output pins in the FPGA chip, a sequential architecture is proposed wherein the DNN inputs enter through only three 8-bit ports. This makes it possible to implement DNNs for image-processing applications. The proposed method is implemented using the Verilog hardware description language on the Xilinx FPGA Virtex-7 xc7v2000t chip. The results show a more than 82% reduction in hardware resources and the minimum rate of power consumption compared to state-of-the-art methods. In addition, the average error rate of the implemented DNN is reduced by 2%.

A Systematic Literature Review on Binary Neural Networks

This paper presents an extensive literature review on Binary Neural Network (BNN). BNN utilizes binary weights and activation function parameters to substitute the full-precision values. In digital implementations, BNN replaces the complex calculations of Convolutional Neural Networks (CNNs) with simple bitwise operations. BNN optimizes large computation and memory storage requirements, which leads to less area and power consumption compared to full-precision models. Although there are many advantages of BNN, the binarization process has a significant impact on the performance and accuracy of the generated models. To reflect the state-of-the-art in BNN and explore how to develop and improve BNN-based models, we conduct a systematic literature review on BNN with data extracted from 239 research studies. Our review discusses various BNN architectures and the optimization approaches developed to improve their performance. There are three main research directions in BNN: accuracy optimization, compression optimization, and acceleration optimization. The accuracy optimization approaches include quantization error reduction, special regularization, gradient error minimization, and network structure. The compression optimization approaches combine fractional BNN and pruning. The acceleration optimization approaches comprise computing in-memory, FPGA-based implementations, and ASIC-based implementations. At the end of our review, we present a comprehensive analysis of BNN applications and their evaluation metrics. Also, we shed some light on the most common BNN challenges and the future research trends of BNN.

Modelling, bifurcation analysis, circuit design and FPGA-based implementation of a new chaotic jerk system exhibiting Hopf bifurcations

Modelling, bifurcation analysis, circuit design and FPGA-based implementation of a new chaotic jerk system exhibiting Hopf bifurcations

Optimized FPGA-Based Implementation of Brain Tumor Detection by Combining K-Means and Grey Wolf Optimization Algorithms

Optimized FPGA-Based Implementation of Brain Tumor Detection by Combining K-Means and Grey Wolf Optimization Algorithms

Highly-Parallel Hardwired Deep Convolutional Neural Network for 1-ms Dual-Hand Tracking

1-ms vision systems represent an extreme case of temporal development in video sensing techniques. Moreover, a 1-ms dual-hand tracking system leverages the dexterous functionality of hands and thus serves as a seamless and intuitive interface for Human-Computer Interaction. Deep CNN is promising for high tracking robustness, however, neither GPU-based nor FPGA-based implementation addresses the tracking task with ultra-high-speed. This paper proposes: (a) A paradigm to directly map a deep CNN as a hardwired circuit, so the entire network runs in parallel and high processing speed is obtained. The network is exempted from memory access since all intermediate neural values are implicitly represented in hardware states. And condensed binarization is used to reduce resource utilization; (b) Hardware design of the hardwired network on FPGA, inside which kernel-adapted convolutional trees are devised to maximize the parallelism. The speed bottleneck of the network is therefore removed by implementing convolutional layers as fine-grained pipelines with unified components; (c) FPGA-GPU hetero complementation, which utilizes an auxiliary GPU network to compensate for accuracy of the FPGA network without affecting its speed. The quick primary results on FPGA are intermittently refined using delayed but accurate hints from GPU. Implementation results show that the proposed method reaches 973fps and consumes merely 1.30ms to process on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$640\times 480$ </tex-math></inline-formula> images, while the accuracy is only 4.7% lower compared with the general method on test sequences. Video demonstrations are available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://wcms.waseda.jp/em/5f9d020f136e7</uri> .

FitNN: A Low-Resource FPGA-Based CNN Accelerator for Drones

Executing deep neural networks (DNNs) on resource-constraint edge devices, such as drones, offers low inference latency, high data privacy, and reduced network traffic. However, deploying DNNs on such devices is a challenging task. During DNN inference, intermediate results require significant data movement and frequent off-chip memory (DRAM) access, which decreases the inference speed and power efficiency. To address this issue, this article presents a field-programmable gate array (FPGA)-based convolutional neural network (CNN) accelerator, named FitNN, which improves the speed and power efficiency of CNN inference by reducing data movements. FitNN adopts a pretrained CNN of iSmart2, which is composed of depthwise and pointwise blocks in the Mobilenet structure. A cross-layer dataflow strategy is proposed to reduce off-chip data transfer of feature maps. Also, multilevel buffers are proposed to keep the most needed data on-chip (in block RAM) and avoid off-chip data reorganization and reloading. Finally, a computation core is proposed to operate the depthwise, pointwise, and max-pooling computation as soon as the data arrive without reorganization, which suits the real-life scenario of the data arriving in sequence. In our experiment, FitNN is implemented on two FPGA-based platforms (both at 150 MHz), Ultra96-V2 and PYNQ-Z1, for drone-based object detection with batch size = 1. The results show that FitNN achieves 15 frames per second (FPS) on Ultra96-V2, with power consumption of 4.69 W. On PYNQ-Z1, FitNN achieves 9 FPS with 1.9 W of power consumption. Compared with the previous FPGA-based implementation of iSmart2 CNN, FitNN increases the efficiency (FPS/W) by 2.37 times.