Efficient hardware mapping of Boolean substitution boxes based on functional decomposition for RFID and ISM band IoT applications

Abstract

This paper investigates three substitution box (S-box) designs for lightweight ciphers. The proposed designs involve functional decomposition, which is preferable as compared to the look-up tables or logic gates-based S-box designs due to their advantages, as outlined in this paper. The aim is to reduce the number of literals at the input of the S-box to achieve resource reduction in the overall circuit design of the encryption algorithms. The proposed S-box architectures provide optimized resource mapping for specific target hardware, and high throughput along with lesser energy consumption compared to state-of-the-art designs. The proposed S-box designs are applied to the substitution layers of symmetric lightweight block ciphers with a standard security level. In order to be fair in comparison, the overall cipher designs are targeted for similar FPGA-based implementation as used in existing works, while the architectures of the individual 4-bit S-boxes are evaluated using SAED90 nm standard cell libraries. The performance of the proposed S-box designs is observed to be superior at RFID and ISM frequency ranges which can be deployed in applications constrained to low resources as well as demanding high performance and medium security.