Four-quadrant Multiplier Research Articles

Signal-based classical emulation of a universal quantum computer

In this paper we present a novel approach to emulating a universal quantum computer with a classical system, one that uses a signal of bounded duration and amplitude to represent an arbitrary quantum state. The signal may be of any modality (e.g., acoustic, electromagnetic, etc), but we focus our discussion here on electronic signals. Unitary gate operations are performed using analog electronic circuit devices, such as four-quadrant multipliers, operational amplifiers, and analog filters, although non-unitary operations may be performed as well. In this manner, the Hilbert space structure of the quantum state, as well as a universal set of gate operations, may be fully emulated classically. The required bandwidth scales exponentially with the number of qubits, however, thereby limiting the scalability of the approach, but the intrinsic parallelism, ease of construction, and classical robustness to decoherence may nevertheless lead to capabilities and efficiencies rivaling that of current high performance computers.

Simulation of four-quadrant four transistors synapse analog multiplier

In this paper, a new implementation of CMOS four-quadrant analogue synapse multiplier circuit for analogue signal processing will be proposed. Especially, it can be used for multi-layer perceptron neural networks. The proposed multiplier is composed of only four transistors and it will multiply two input currents and produces an output current. The global multiplier circuit consists of 10 transistors, but only four of them will be implemented inside the synapse, while the others will be implemented inside the input and the neuron. The main characteristics of the proposed circuit are the small silicon area and the low power consumption. A comparison among some other multipliers will be presented.

A New Highly Accurate CMOS Current-Mode Four-Quadrant Multiplier

A new CMOS current-mode four-quadrant analog multiplier is presented. The design is based on the square-difference approach using short-channel MOSFETs operating in saturation region and a rectifier. The squaring circuit used is free of error due to carrier mobility reduction and hence an accurate multiplier is achieved. Tanner T-spice is used to confirm the functionality of the proposed design using 0.18μm TCMS CMOS process technology. Simulation results shows that the relative error is 1.8% and –3dB frequency is 230MHz.

CMOS design of a four-quadrant multiplier based on a novel squarer circuit

In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of ±10 μA demonstrate a ?3 dB bandwidth of 24.5 MHz, 475 μW as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.

Ultra-low voltage CMOS current-mode four-quadrant multiplier

A novel configuration of a four-quadrant current multiplier is introduced in this paper. The realisation is achieved through the utilisation of the voltage translinear principle; the derived topology simultaneously offers the attractive benefits of ultra-low voltage operation and reduced DC power dissipation, in comparison with the corresponding already published multipliers. The above have been achieved without increasing the circuit complexity. The behaviour of the multiplier has been evaluated through simulation results, using the Analog Design Environment and the design kit provided by the Taiwan Semiconductor Manufacturing Company 180 nm complementary metal-oxide semiconductor process.

Embedded Power and Energy Measurement System Based on an Analog Multiplier

This paper deals with the development of an analog electronic wattmeter based on a high-accuracy electronic four-quadrant multiplier and appropriate amplifying and averaging circuits. The proposed instrument presents a simple design and is constructed using commercially available components. Its main advantage is that it can be integrated with the signal conditioning circuit, obtaining low cost, high resolution, and reduced dimensions. It can measure in circuits with very low power factors and nonsinusoidal waveforms. The implemented prototype is a portable laboratory instrument, integrated with a digital system capable of processing the signals, and displaying the main parameters of both electric power and energy. It has been designed to easily integrate the main blocks in that either industrial or civil equipment requiring the power measurement for monitoring or control purposes. A Fluke 6100A power standard is used to calibrate the wattmeter over a wide range of current magnitudes and widths and at power factors down to 0.02; several results are reported and discussed.

Single OTRA Based Analog Multiplier and Its Applications

This paper presents an analog multiplier using single operational transresistance amplifier (OTRA). The proposed circuit is suitable for integration as it does not use any external passive component. It can be used as a four-quadrant multiplier. Theoretical propositions are verified through PSPICE simulations using 0.5 μm CMOS parameters provided by MOSIS (AGILENT). The simulation results are in close agreement with theoretical predictions. The workability of the proposed multiplier is also tested through two applications, namely, a squarer and an amplitude modulator.

FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS

This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.

A Translinear, Log-Domain FPAA on Standard CMOS Technology

A field-programmable analog array (FPAA) using a standard-CMOS wide-dynamic-range translinear element (TE) is introduced. The FPAA configurable analog blocks (CABs) are based on a reconfigurable translinear cell (RTC), capable of implementing the basic circuit elements required by translinear and log-domain circuit design. The interfacing is provided by an I/O programmable cell, which allows for easier connectivity between the signal-processing core and the external circuitry. As a proof-of-concept, a 5 × 5 RTC FPAA testchip was implemented in 0.35- μm CMOS technology. A set of various circuit primitives, such as one- and four-quadrant multipliers, an Euclidean distance operator and a fourth-order log-domain filter, were mapped on the chip in order to demonstrate the versatility of the approach. FPAA bandwidth reaches 20 MHz with a power consumption of 30 μW/TE and precision errors below 3%.

Versatile analog squarer and multiplier free from body effect

This paper proposes the analog CMOS squarer and the four-quadrant analog CMOS multiplier. The major advantages of the proposed circuits are low voltage supply, multifunction of output, and insensitive to the threshold voltage variation caused by body effect. The versatile squarer has two inputs (V in and I in ). Its output can be the square of V in or the square of I in . The versatile four-quadrant multiplier has four inputs (V X , I X , V Y , and I Y ). Its output can be the product of V X and V Y , the product of I X and I Y , the product of V X and I Y , or the product of V Y and I X . Therefore, the proposed circuits can be applied more than conventional circuits and have good performance. Second-order effects and frequency response are analyzed. Simulation results have verified the workability of the circuits. Experimental results are done to confirm the operation of the circuits.

0.65 V class-AB current-mode four-quadrant multiplier with reduced power dissipation

A class-AB CMOS current-mode four-quadrant multiplier with an improved biasing scheme is introduced in this letter. Compared to the corresponding already published topology, the proposed multiplier offers a significant reduction of power dissipation without increasing the circuit complexity. The behavior of the proposed topology has been verified through simulation results using typical parameters of a 0.13 μm CMOS technology.

Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS Inverters

Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS InvertersThe paper presents quarter-square analog four-quadrant multipliers, based on proprietary architecture using four CMOS inverters. The most important upgrade on already published own circuit implementation is the use of the same inverter "core" of the circuit with completely redesigned auxiliary and steering blocks. Two variants of new driving peripherals are considered: one with differential pair, the second with CMOS inverters. The proposed circuit solutions are suitable for RF applications in communication systems due to simple architecture comprising building blocks with RF CMOS transistors having sufficiently large biasing currents. Postlayout simulation results done on the basis of 180nm CMOS UMC Foundry Design Kit are also presented.

Multiplier, frequency doubler and squarer circuits based on voltage controlled resistors

In this paper, a floating voltage controlled positive resistor (FVCPR) with its applications is studied in detail. Compared to previously reported resistor topologies consisting of excessive number of CMOS transistors and dissipating much power, the advantages of the FVCPR are to employ only two CMOS transistors in triode region, and to dissipateal most no power when applied input voltage/current is zero. The FVCPR has two control voltages for electronically changing the value of its positive resistance. Also, one of the control voltages can be used to tune the resistive component while keeping the other one constant. A transadmittance-mode (TM) four-quadrant multiplier, a TM sinusoidal frequency doubler and a TM squarer circuit are derived from the FVCPR as application examples. Some time and frequency domain analyses with SPICE simulation program and an experimental test result are included to exhibit the work ability and effectiveness.

CMOS multiplier based on the relationship between drain current and inversion charge

The authors propose a four-quadrant multiplier based on a core cell that exploits the general relationship between the saturation current of an MOS transistor and the source inversion charge density, valid from weak to strong inversion. The advantages of the proposed circuit are simplicity, low distortion and feasibility of low-voltage operation. Experimental results in a 0.35 µm CMOS prototype indicate 1 mA consumption for 1 MHz bandwidth, and distortion level below 1% for an input current of 80% of the full-scale range. The multiplier core area is around 10 000 µm2.

Ultra-low-power, class-AB, CMOS four-quadrant current multiplier

A class-AB four-quadrant current multiplier constituted by a class-AB current amplifier and a current splitter which can handle input signals in excess of ten times the bias current is presented. The proposed circuit operation is based on the exponential characteristic of BJTs or subthreshold MOSFETs. The multiplier is designed using the latter devices and achieves very low power consumption. Simulation results show that from a 0.65 V supply, the proposed circuit consumes 12.4 nW static power while less than 30 dB total harmonic distortion is achieved for an input modulation index up to 10.

A new high speed and low power four-quadrant CMOS analog multiplier in current mode

In this paper a new CMOS current-mode four-quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3 V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 μ m standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.1%, a THD of 0.97% in 1 MHz, a - 3 dB bandwidth of 41.8 MHz and a maximum power consumption of 0.34 mW.

Design of a Simple Current-Mode Multiplier Topology Using a Single CCCII+

In this paper, an analog current-mode (CM) multiplier circuit employing a single plus-type second-generation current-controlled conveyor (CCCII+) and a grounded resistor is proposed. The developed circuit can provide two-quadrant multiplication, four-quadrant multiplication, and frequency doubling all from the same topology with the selection of the applied input currents. In addition to the signal limitations of the multiplier configuration, the nonideality effects of the CCCII+ and the nonideal gain and parasitic impedance effects on the proposed circuit are investigated. The realized circuit is simulated with SPICE to exhibit its performance. In addition, a CM multiplier derived from the proposed multiplier is set up with commercially available active components to easily perform its experimental test.

A current-mode CMOS fuzzy logic controller

In this paper, design and simulation of a current-mode CMOS Fuzzy Logic Controller (FLC) is presented. The proposed controller is composed of Membership Function Circuit (MFC), fuzzy inference engine with min-product method and current-mode defuzzification circuit. MFC has a new architecture that generates basic four membership functions (trapezoidal, triangle, Z-shape and S-shape). These membership functions are simply tuneable by adjusted two voltages via setting some analogue switches in a shape/label select circuit block which is called programming unit. Also, a novelty designed current-mode defuzzification circuit is based on current-mode four-quadrant multipliers that have been constructed simple current squarer and substractor circuits. The proposed current-mode CMOS FLC has been simulated and verified for two inputs, one output and nine tuneable fuzzy rules by using PSPICE program with MIETEC 1.2 µm design parameters. The proposed architecture has an operation speed of 6.25 MFLIPS (6.25 × 106 Fuzzy Logic Inference per Second).

A Comparison of Distortion Analyses Based on Volterra Series and Steady State Algorithm

The most accurate way for computing the distortion coe-cients is to flnd a steady state period of the signal, and then to determine spectrum by means of fast Fourier transform. In the paper, main features of a reliable and e-cient algorithm for determining the steady state are described. However, even such accelerated method often needs a time-consuming numerical integration over many periods of the faster signal. For this reason, an e-cient method for a fast estimation of the main distortion coe-cients is also presented which does not contain frequent imperfections in the algorithm implementations. The algorithm uses higher-order Volterra series in a simple multistep algorithm which is compatible with a typical structure of the frequency do- main part of software tools. Both methods are compared by analyses of the main intermodulation products of a low-voltage low-power CMOS RF four-quadrant multiplier. A natural and accurate method for determining intermodulation products is to flnd a steady state period, and then to compute the spectrum of that signal by means of fast Fourier transform. This algorithm has been implemented into our original software tool C.I.A. (Circuit Interactive Analyzer) with a possibility of the automatic determination of the unknown period of autonomous circuits. Basic theory of the steady state analysis is described in (1), some improvements especially for automating the procedure for the autonomous circuits are deflned in (2). As the implemented method for a numerical integration (which is necessary for the steady state algorithm) is accurate and very ∞exible (it is based on an e-cient recurrent form of Newton interpolation polynomial (4,5)), computed intermodulation products are available even for higher orders. However, the numerical integration must still be performed over many periods of the faster signal and therefore the analysis is time-consuming. For this reason, another method for a fast estimation of the main interpolation products has also been implemented based on Volterra series. A brief introduction to using the Volterra series is shown in (6), a more comprehensive analysis can be found in (7). A disadvantage of many of the implementations of the Volterra series consists in a creation of a new (relatively large and isolated) block of the program. In this paper, a simple modiflcation of the method is deflned, which is compatible with the frequency domain part of the program | the algorithm is built into and uses a relatively large part of the AC analysis. 2. GENERAL DESCRIPTION OF THE STEADY STATE ALGORITHM

A Precise Four-Quadrant Multiplier with Subnanosecond Response

Reprinted from the IEEE Journal of Solid-State Circuits, Vol. 3, No. 4 (1968), pp. 365-373. Among the most signficant presentations in the 50-year history of the ISSCC, Barrie Gilbert's classic paper has become the fifth most frequently cited JSSC article and the first to be cited over 100 times. His brilliant insight was in recognizing that the dependability of a bipolar transistor's nonlinearity can be exploited to realize exceptionally linear systems.