Simulation of four-quadrant four transistors synapse analog multiplier

Abstract

In this paper, a new implementation of CMOS four-quadrant analogue synapse multiplier circuit for analogue signal processing will be proposed. Especially, it can be used for multi-layer perceptron neural networks. The proposed multiplier is composed of only four transistors and it will multiply two input currents and produces an output current. The global multiplier circuit consists of 10 transistors, but only four of them will be implemented inside the synapse, while the others will be implemented inside the input and the neuron. The main characteristics of the proposed circuit are the small silicon area and the low power consumption. A comparison among some other multipliers will be presented.