Evaluation of power efficient adder and multiplier circuits for FPGA based DSP applications

Abstract

This paper describes the design and implementation of low power arithmetic circuits for digital signal processing (DSP) applications, using Xilinx XC5VLX30 (Virtex-5) field programmable gate array (FPGA) devices. DSP is a highly demanding application domain in the present day technology wherein the demands for enhanced performance and reduced resource utilization have increased over the years. Recent advancements in FPGA design technology through the incorporation of DSP functional blocks along with the inherent FPGA features like high flexibility through reconfiguration, reusability, moderate cost and feature extension has resulted in FPGA(s) becoming the preferred platform for evaluating and implementing DSP. The arithmetic circuits for addition and multiplication are the core of any DSP hardware as all the operations in DSP domain are a combination of these. In this work we have implemented the various forms of adder and multiplier circuits on FPGA, to have an analysis for finding out the most suitable arithmetic circuits for FPGA based DSP implementation. We present an analysis of our implementation results in respect to delay, power requirement and implementation costs of the different 8, 16, 32 and 64 bit circuits that can be realized for implementing the basic fixed-point arithmetic units in FPGA.