Evaluation of Power Efficient FIR Filter for FPGA based DSP Applications

Abstract

This paper describes the design and implementation of low power FIR filter for digital signal processing (DSP) applications, using Xilinx 6V1X130T1FF1156 (Virtex-6 Low Power) field programmable gate array (FPGA) devices. DSP is a highly demanding application domain in the present day technology wherein the demands for enhanced performance and reduced resource utilization have increased over the years. Recent advancements in FPGA design technology through the incorporation of DSP functional blocks along with the inherent FPGA features like high flexibility through reconfiguration, reusability, moderate cost and feature extension has resulted in FPGA(s) becoming the preferred platform for evaluating and implementing DSP. In this work we have implemented the various forms of FIR filter on FPGA and compared their performances in terms of delay, frequency of operation, resource utilization and power. To the best of our knowledge our work is first of its kind in respect to Virtex-6 FPGA devices. Our research paves the way for selecting the most suitable FIR filter architecture for DSP implementation using Virtex-6 FPGA.