Four-quadrant Multiplier Research Articles

Design and applications of a CMOS analog multiplier cell using the differential difference amplifier

This paper presents design techniques for a wide input range CMOS differential difference amplifier (DDA) and discusses its application as a basic block in the implementation of a simple four-quadrant multiplier cell. The cell can be configured as an amplitude modulator or a one-over circuit, which are widely used in many analog signal processing applications. The DDA can also be reconfigured as an opamp, and hence can be used to design many of the opamp-based multiplier circuits. The DDA amplitude modulator (AM) uses a transistor and a resistor as the only components external to the DDA. A DDA one-over circuit, which provides an output proportional to the inverse of the input, is also achieved with the same level of simplicity. High-frequency effects due to the DDA's finite gain-bandwidth (GB) and MOS parasitic capacitances are investigated. Experimental results obtained from a 2µm CMOS MOSIS chip are given.

A four-quadrant CMOS analog multiplier for analog neural networks

A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 /spl mu/m CMOS process. Experimental results obtained from it are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

CMOS four-quadrant multiplier using bias feedback techniques

A new wide-range CMOS four-quadrant multiplier using the bias feedback techniques is presented. Simulation results show that for a power supply of /spl plusmn/5 V, the linear range is over 14 V and the linearity error is less than 1% over a 13 V input range. Experimental results show that the linear range is over /spl plusmn/1 V. The results will be useful in analog signal processing applications. >

Configurable CMOS multiplier/divider circuits for analog VLSI

The design of five simple CMOS opamp based multipler/divider circuits is presented. Each two opamp and six MOSFET transistor circuit simultaneously achieves four-quadrant multiplication and division. Applications of the new circuits in analog signal processing and neural networks are discussed. The multiplier/divider circuits are all insensitive to MOS intrinsic parasitic capacitances. They do, however, exhibit different sensitivities to opamp finite unity-gain bandwidth. These sensitivities may be mitigated using the configurability property of the circuits. Finally experimental results are provided to support some of the theoretical claims.

A bipolar four-quadrant analog quarter-square multiplier consisting of unbalanced emitter-coupled pairs and expansions of its input ranges

A bipolar four-quadrant analog multiplier based on the quarter-square technique, which is constituted from unbalanced emitter-coupled pairs, and some methods for extending the input voltage range, are described. The building blocks for the circuit consist of an unbalanced emitter-coupled pair with different emitter areas, an emitter-coupled pair with an input bias offset, and an unbalanced emitter-coupled pair with unbalanced emitter degeneration. A basic squaring circuit is realized from two identical unbalanced emitter-coupled pairs with emitter area ratio K and cross-coupled inputs and parallel-connected outputs. The quarter-square multipliers proposed in this paper can operate under low supply voltage (typically >

New simulated inductor using four-quadrant analogue multipliers

An integrated simulated inductor was proposed by Qiu (1991 QIU , D. , 1991 , Circuit design of an integrable simulated inductor and its applications . I.E.E.E. Transactions on Instrumentation and Measurement , 40 , 902 – 907 .[Crossref] , [Google Scholar]). It was composed of discrete components for use before its realization as a monolithic integrated circuit. But it was a trouble to need so many matched pair transistors. A satisfactory solution is to use ready-made IC four-quadrant analogue multipliers to form the simulated inductor. The present simulated inductor is different from the former in circuit construction and expression form although they are simular in basic principle. Its features make it suitable for practical applications as a circuit element of a sine-wave oscillator or a filter with linear voltage control characteristics in the low or very-low frequency ranges. A typical example is to build a sweep-frequency signal source to determine the frequency response of a linear network working in a very-low frequency range, which has been verified experimentally.

Four-quadrant optical matrix–vector multiplication machine as a neural-network processor

Optical processors for neural networks are primarily fast matrix-vector multiplication machines that can potentially compete with serial computers owing to their parallelism and their ability to facilitate densely connected networks. However, in most proposed systems the multiplication supports only two quadrants and is thus unable to provide bipolar neuron outputs for increasing network capabilities and learning rate. We propose and demonstrate an opto-electronic four-quadrant matrix-vector multiplier that can be used for feed-forward neural-network recall and learning. Experimental results obtained with common commercial components demonstrate a novel, useful, and reliable approach for fourquadrant matrix-vector multiplication in general and for feed-forward neural-network training and recall in particular.

CMOS four-quadrant multiplier using bias offset crosscoupled pairs

A CMOS four-quadrant multiplier using bias offset crosscoupled pairs is presented. Simulation results show that for a power supply of ±5 V, the linearity error is less than 1% over a ±2.5 V input range. The effect of mobility reduction is also analysed. The results will be useful in analogue signal processing applications.

Highly linear four quadrant analogue BiCMOS multiplier for ±1.5 V supply operation

A highly linear four-quadrant analogue BiCMOS multiplier is presented. It operates with ±1.5V supplies and with 2V peak to peak input and output signal wings. It is based on the use of crosscoupled, voltage biased differential pairs. Experimental results of a CMOS test chip are presented that confirm the proposed structure.

A simple CMOS analog four-quadrant multiplier

A simple CMOS circuit which performs analog four-quadrant multiplication is described. Transconductance as well as voltage-mode operation is practicable. The basic circuit consists of only two transistors, at least one of which is depletion-mode. We analyze sources of error in the multiplier, and suggest additional circuitry to improve performance. The circuit has been fabricated in thin-film silicon-on-sapphire and test results are reported. Error relative to full-scale output, and total harmonic distortion with individual multiplicands varied sinusoidally, were both observed to be on the order of 1% to 3% with full-scale inputs.

Wide-band symmetrical analog multiplier IC for coherent optical-fiber receivers operating up to 10 Gb/s

A versatile analog four-quadrant multiplier IC with large bandwidth (DC to 6 GHz and 10 Gb/s) and large dynamic range is presented. It was mainly developed for differential-phase-shift-keying (DPSK) phase demodulator and polarization diversity receivers in coherent optical-fiber transmission systems. The circuit consumes 450 mW and only needs a single power supply of -5 V. The circuit principle used allows exact symmetry with respect to both linear inputs, which reduced multiplication errors. In the intended application, especially, the time jitter and the offset voltage of the output pulse patterns are reduced to negligible values. The IC was realized in a 1.25- mu m double-polysilicon bipolar technology. >

Four-quadrant multiplier combining sigma-delta and multirate processing techniques

A mixed analogue-digital solution combining sigma-delta and multirate processing techniques is proposed for realising four-quadrant multipliers. This overcomes the major limitations of purely analogue circuits and still achieves the attractive benefits of low power consumption and small chip size which cannot be afforded using digital signal processing techniques together with auxiliary analogue-digital and digital-analogue convertors.

A nonlinear CMOS analog cell for VLSI signal and information processing

A simple reconfigurable continuous-time nonlinear CMOS building block for analog VLSI applications is presented. The new block is introduced as a basic analog cell for the implementation of analog VLSI systems. It simultaneously achieves four-quadrant multiplication and division. Its applications in both analog signal and information processing are discussed. These include multiplication, signal squaring, division, signal inversion, amplitude modulation, RMS-DC conversion, and neural computing. Using the new cell, a MOS VLSI implementation of a feedback/feedforward neural network is developed which achieves the scalar product of two n-tuple vectors by 4(n+1) MOS transistors and one operational amplifier. To verify the versatility of the new cell and its applications, experimental results obtained from a test chip that was fabricated using the MOSIS 2- mu m CMOS process are included.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Comments on 'A CMOS four-quadrant multiplier': effects of threshold voltage

For the original article see ibid., vol.SC-21, no.3, p.430-5 (1986). A CMOS four-quadrant multiplier based on 12 transistors was proposed by K. Bult and H. Wallinga in the above-titled paper using four floating-well transistors to keep V/sub T/ constant. It is shown analytically by the commenter that the floating wells can be avoided with little penalty on distortion, but with reduction in signal output. A four-transistor multiplier is also analyzed. >

A single-chip bipolar AGC amplifier with large dynamic range for optical-fiber receivers operating up to 3 Gbit/s

A complete automatic gain control (AGC) main amplifier for gigabit-per-second optical-fiber transmission system was carefully designed and integrated on a single chip, using a standard 2- mu m silicon bipolar technology. Gain control was performed by use of the four-quadrant multiplier principle. The amplifier is characterized by a maximum voltage gain of 40 dB, a large input dynamic range of 40 dB, a maximum bit rate of 3 Gb/s, and a gain-independent 3-dB cutoff frequency of 2.5 GHz. The experimental results agree very well with the simulation predictions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A simple analogue multiplier with analogue/digital output

A simple circuit for the four-quadrant multiplication of voltage signals is described. The output of the multiplier is suitable for analog as well as digital applications. Experimental results obtained are in agreement with the theory developed. >

Linear sinusoidal VCO

This paper presents a sinusoidal oscillator whose frequency of oscillation bears a linear relationship with the controlling voltage Vx. The basic configuration incorporates two four-quadrant analogue multipliers in conjunction with RC network of which two capacitors are grounded. The circuit is found to show an ultra-low distortion output. The realization of the basic configuration uses two grounded capacitors which are suitable for LSI implementation of the oscillator circuit.

A ±5-V CMOS analog multiplier

A four-quadrant CMOS analog multiplier is presented. The device is nominally biased with /spl plusmn/5-V supplies, has identical full-scale single-ended x and y inputs of /spl plusmn/4 V, and exhibits less than 0.5% nonlinear error at 75% of full-scale swing. Operation with supplies as low as /spl plusmn/2.5 V is also possible. A comparison of theoretical and experimental results obtained from fabrication of the multiplier in a 3-/spl mu/m p-well CMOS process is made.

New four-quadrant CMOS analogue multiplier

The letter describes a new four-quadrant CMOS analogue multiplier with a simple circuit configuration. This multiplier is based on the current/voltage characteristics of MOS transistors operating in the triode region. The simulation result shows less than 1% distortion for both input signals of 4Vpp when supply voltages of ± 5V are used.

Integrated MOS four-quadrant analog multiplier using switched capacitor technology for analog signal processor ICs

A fully integrated four-quadrant analog multiplier (4-QAM) based on switched capacitor technology is developed using a short-channel MOSFET fabrication process for realization of high-speed and high-density analog signal processor ICs. This 0.6-mm/SUP 2/ 4-QAM, consisting of a pair of MOSFETs, three op. amps., and a switched capacitor circuit, does not require any external circuits to perform the four-quadrant analog multiplication. The characteristics are measured, showing a total harmonic distortion of less than -50 dB for two input signals of 1 V/SUB p-p/, a dynamic range of more than 75 dB, and an operation speed of more than 2-MHz clock rate. In addition, the principal factors of the nonlinear distortion are analyzed. Application of the 4-QAM to convolvers and correlators is also discussed.