Forward Biased Safe Operating Area Research Articles

A fast-switching low-loss field-stop IGBT with dual control gate of SIPOS material

A fast-switching low-loss field-stop insulated gate bipolar transistor with a dual control gate (DIGBT) of a semi-insulating polycrytalline silicon (SIPOS) material is proposed in this paper. Because the SIPOS has uniform high resistance, it has an approximate linear electric potential distribution. When DIGBT conducts, the higher electric potential on SIPOS causes the P-type drift region (P-drift) to generate an inversion layer of electrons, adjusting the number of carriers and making the generation of non-equilibrium carriers no longer dependent on the doping concentration in P-drift (Nd) but on the electric potential distribution on SIPOS. Therefore, it can solve the contradiction among the breakdown voltage, forward voltage drop [VCE(sat)], turn-off time (toff), and turn-off loss (Eoff) caused by the Nd. Through Technology Computer Aided Design (TCAD) simulation, the VCE(sat) of DIGBT is 30.6% lower than that of SJFS IGBT. Meanwhile, DIGBT reduces the toff by 62.8% while reducing the Eoff by 83.0% compared to SJFS IGBT. In addition, the static latch-up I–V and the forward biased safe operating area of the DIGBT have been significantly improved. This paper adjusts the number of carriers through the characteristics of SIPOS material, enabling the above-mentioned physical phenomena to be applied in insulated gate bipolar transistor power devices and achieving device performance breakthroughs.

A novel 4H–SiC IGBT with double gate PMOS for improving the switch controllability and FBSOA

In this work, a 4H–SiC insulated-gate bipolar transistor (IGBT) with double gate PMOS (DGPMOS) is proposed. In the on-state, DGPMOS IGBT can form a hole barrier, thus reducing the on-state voltage (VON). During the turn-on and turn-off transients, DGPMOS IGBT can form the extra hole extraction paths. This helps to reduce the turn-off loss (Eoff) and the gate displacement current (IG_dis). The simulation results show that compared with GS IGBT, the VON of DGPMOS IGBT is decreased by 58.04% under the same Eoff. Compared with PMOS IGBT, DGPMOS IGBT achieves better controllability in turn-on dIC/dt and peak turn-on current (Imax). At the same turn-on loss (Eon), the maximum reverse recovery dVKA/dt is lowered by 26.67%, and the electromagnetic interference (EMI) noise is suppressed. In addition, because DGPMOS IGBT has a small saturation current density (Jsat), its forward bias safe operating area (FBSOA) is greatly improved.

Novel majority carrier accumulation insulated gate bipolar transistor with Schottky junction

Insulated gate bipolar transistor (IGBT) is the core of modern power semiconductor device, and has been widely used due to its excellent electrical characteristics. A novel majority carrier accumulation mode IGBT with Schottky junction contact gate semiconductor layer (AC-SCG IGBT) is proposed and investigated by TCAD simulation in this article. When the AC-SCG IGBT is in the on-state, a forward bias is applied to the gate. Due to the very low forward voltage drop (<i>V</i><sub>F</sub>) of the Schottky barrier diode, the potential of the gate semiconductor layer is almost equal to the gate potential, which can accumulate a large number of majority carrier electrons in the drift region. In addition to the electrons existing, these accumulated electrons increase the conductivity of the drift region, thus significantly reducing <i>V</i><sub>F</sub>. Therefore, the doping concentration of the drift region is not limited by <i>V</i><sub>F</sub>. The lightly doped drift region can make AC-SCG IGBT have a higher breakdown voltage (BV). Moreover, it also reduces the barrier capacitance in the turn-off process, thus the overall Miller capacitance is small, which can quickly turn off and reduce the turn-off time (<i>T</i><sub>off</sub>) and turn-off loss (<i>E</i><sub>off</sub>). The simulation results indicate that at the BV of 600 V, the <i>V</i><sub>F</sub> of 0.84 V for the proposed AC-SCG IGBT is reduced by 46.2% compared with that for the conventional IGBT (<i>V</i><sub>F</sub> of 1.56 V). The <i>E</i><sub>off</sub> of the AC-SCG IGBT (0.77 mJ/cm<sup>2</sup>) is reduced by 52.5% compared with that for the conventional IGBT (1.62 mJ/cm<sup>2</sup>), and the <i>T</i><sub>off</sub> (155.8–222.7 ns) is reduced by 30%. The contradiction between <i>V</i><sub>F</sub> and <i>E</i><sub>off</sub> is eliminated. In addition, the proposed AC-SCG IGBT has a better anti-latch-up capability and is coupled with its higher BV, so it has a larger forward biased safe operating area (FBSOA). The proposed novel structure meets the development requirements for future IGBT device performance, and has great significance for guiding the development of the power semiconductor device field.

An 800V ultra-low loss field-stop insulated gate bipolar transistor with extended polysilicon gate structure

This paper proposed a Insulated Gate Bipolar Transistor with extended polysilicon gate structure (EPG IGBT) based on P-type drift region (P-Drift), which has electron inverse and accumulation layer. It designs the gate as an extended gate structure with a Bipolar Junction Transistor (BJT), extending into the collector region, and the BJT is always blocked during the switching process. When the EPG IGBT is conducting, the Nj region has a constant positive voltage, which causes the P-Drift to form an electron inversion layer and conduct. Through TCAD simulation, the EPG IGBT maintained the same Breakdown Voltage and turn-off time, while reducing its forward voltage drop (VCE(sat) = 0.98 V) and turn-off loss (Eoff = 0.89 mJ/cm2) by 36 % and 44 %, respectively, compared with FSSJ IGBT of the same process (VCE(sat) = 1.53 V, Eoff = 1.58 mJ/cm2). In addition, the static latch-up I–V and Forward Biased Safe Operating Area (FBSOA) of the EPG IGBT have been significantly improved, providing a new approach for optimizing IGBT.

캐리어 수명시간과 온도에 따른 수직형 절연 게이트 바이폴러 트랜지스터의 Forward Biased Safe Operating Area를 위한 설계 및 시뮬레이션

캐리어 수명시간과 온도에 따른 수직형 절연 게이트 바이폴러 트랜지스터의 Forward Biased Safe Operating Area를 위한 설계 및 시뮬레이션

Simulation study of a novel thin layer SOI carrier-stored TLIGBT with self-biased pMOS

A novel thin layer Silicon-On-Insulator (SOI) carrier-stored (CS) trench lateral insulated gate bipolar transistor (TLIGBT) with P-shield layer and self-biased pMOS is proposed. The potential of the P-shield layer is clamped by the self-biased pMOS, which transfers the reverse voltage-sustaining position from the P-base/carrier-stored layer (CSL) junction to the P-shield/N-drift junction during the off-state. Therefore, the doping concentration of the CSL (NCS) can be increased by several orders of magnitude to decrease the on-state voltage drop (Von) without jeopardizing the breakdown voltage. Moreover, the self-biased pMOS shunts most of the hole current during on-state when the voltage of the collector is further increased, which clamps the drain-to-source voltage of the intrinsic nMOS. Then, low saturation current and large forward biased safe operating area are obtained for the proposed TLIGBT. The simulation results reveals that the turn-off loss (Eoff) of the proposed TLIGBT at Von ≈ 1.35 V is reduced by 25.4% and 41.9% compared with those of the conventional TLIGBT A and conventional TLIGBT B, respectively. Besides, the saturation current density of the proposed TLIGBT is reduced by over 44% compared with those of the conventional ones. Consequently, the short-circuit withstand time is improved by over 164%.

Investigation on Self-Adjust Conductivity Modulation SOI-LIGBT Structure (SCM-LIGBT) for Monolithic High-Voltage IC

A novel composite device structure named self-adjust conductivity modulation lateral insulated gate bipolar transistor (SCM-LIGBT), including normal LIGBT region (NLT region), the EM-nMOS region (ENM region), and the series diode region (DIO region), is proposed in this paper. By adding the enhanced-mode nMOS region and the series diodes region, the parasitic NPN transistor (NPN) bipolar structure in the normal LIGBT structure can be triggered in on-state and the conductivity modulation is dramatically enhanced, which leads to the improvement on the current capability and the forward voltage. In addition, due to the base voltage of the parasitic NPN bipolar structure in the proposed device can be clamped at the forward threshold of the series diodes, therefore the latch-up issues can be immunized to guarantee the forward-biased safe operating area. Numerous simulations and measurements are presented to investigate the electrical characteristics of the proposed structure. The length of the fabrication SCM-LIGBT is $78.5~\mu \text{m}$ , and the width of the DIO and NLT is 830 $\mu \text{m}$ , while the width of the ENM is $4100~\mu \text{m}$ . The results demonstrate that the proposed SCM-LIGBT achieves a high-current capability ( ${J}_{A})$ of 2428 A/cm2 at ${V}_{G}= 10$ V, a low on-state voltage drop of 1.15 V at ${J}_{A}= 150$ A/cm2 with its breakdown voltage of 590 V.

High-Voltage Electron Injection Enhanced TC-LIGBT on 1.5- $\mu \text{m}$ -Thin SOI Layer for Reducing the Forward Voltage Drop

In this paper, a new high-voltage electron injection enhanced tridimensional channel lateral insulated gate bipolar transistor (EIETC-LIGBT) on 1.5- $\mu \text{m}$ -thin silicon-on-insulator (SOI) layer is proposed to reduce the forward voltage drop. Based on the previous TC-LIGBT we have proposed, an extra floating p-layer is added at the emitter side of the proposed EIETC-LIGBT. The region locating between the separated p-body cells and the floating p-layer is the high doped n-type electron injection efficiency modulation (EIEM) region. Above the EIEM region, several virtual polygate structures connected to the emitter are fabricated between the separated p-body cells and the floating p-layer. The highly doped EIEM region can help the proposed structure to reduce the forward voltage drop by increasing the electron injection efficiency. The virtual gate structures are contributed to the forward-biased safe operating area of the proposed structure. By optimizing the doping of the EIEM region and the width of the virtual gate structures, an EIETC-LIGBT with the forward voltage drop of 3.4 V at $V_{\mathrm {{GE}}}= 10$ V and $J_{\mathrm {{CE}}}= 100$ A/cm $^{\mathrm {{2}}}$ can be achieved, which has an improvement of 17% compared with the previous TC-LIGBT structure on the same thin SOI layer without sacrificing the current capability.

Theory and optimization of the power super junction device

Based on the optimization idea of the electric field from the surface to the bulk, this paper summarizes the basic theory and the two types of analytical optimization methods of the super junction (SJ) device. The essential difference between the SJ and the conventional power MOS structure is: the former is the junction-type voltage sustaining layer with the periodic N/P dopings and the later is the resistance-type voltage sustaining layer with the single conductive type. The positive and negative charges satisfying the charge balance are introduced into the SJ voltage sustaining layer, which causes the two-dimensional electric field to realize the optimization from the surface to the bulk. The paper gives the concepts of the charge and potential electric fields, analyzes the non-full depletion and full depletion modes, introduces the mechanism of the transient process and forward biased safe operating area, discusses the equivalent substrate model and the optimized substrate conditions. Finally, the minimum specific on-resistance R on,min optimization methodology is proposed to give the R on,min for a given breakdown voltage V B. R on of the SJ is decreased significantly compared to that of the conventional power MOS with the same V B. The R on -V B relationship changes from the R on∝ V B2.5 to V B1.32 even V B1.03, leading to the SJ as the “milestone in high voltage power MOS device”

Small-sized silicon-on-insulator lateral insulated gate bipolar transistor for larger forward bias safe operating area and lower turnoff energy

This Letter presents a novel small-sized lateral insulated gate bipolar transistor on silicon-on-insulator substrate (SOI-LIGBT), which features a lowly doped p -type pillar alongside the oxide trench in the drift region. The variation in vertical doping termination technology is also proposed for the first time. The p -pillar layer leads to electric field reshaping in the y -direction, and homogenises current flow lines under the gate and cathode. It results in a very wide forward bias safe operating area (FBSOA) for the proposed SOI-LIGBT, which is obviously improved by over 50% compared with the deep-oxide trench SOI-LIGBT (DT SOI-LIGBT). Moreover, at the same forward voltage drop of 1 V, the turnoff energy loss for the proposed SOI-LIGBT is reduced by 28.5 and 81.2% compared with those of DT SOI-LIGBT and the conventional SOI-LIGBT, respectively.

200 V Superjunction N-Type Lateral Insulated-Gate Bipolar Transistor With Improved Latch-Up Characteristics

This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) of 2 V at 300 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The latch-up current density is 1100 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> . The latest design shows a latch-up current density of 1195 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The enhanced robustness against static latch-up leads to a better forward bias safe operating area.

Insulated gate bipolar transistor with trench gate structure of accumulation channel

An accumulation channel trench gate insulated gate bipolar transistor (ACT-IGBT) is proposed. The simulation results show that for a blocking capability of 1200 V, the on-state voltage drops of ACT-IGBT are 1.5 and 2 V at a temperature of 300 and 400 K, respectively, at a collector current density of 100 A/cm2. In contrast, the on-state voltage drops of a conventional trench gate IGBT (CT-IGBT) are 1.7 and 2.4 V at a temperature of 300 and 400 K, respectively. Compared to the CT-IGBT, the ACT-IGBT has a lower on-state voltage drop and a larger forward bias safe operating area. Meanwhile, the forward blocking characteristics and turn-off performance of the ACT-IGBT are also analyzed.

Trench gate IGBT structure with floating P region

A new trench gate IGBT structure with a floating P region is proposed, which introduces a floating P region into the trench accumulation layer controlled IGBT (TAC-IGBT). The new structure maintains a low on-state voltage drop and large forward biased safe operating area (FBSOA) of the TAC-IGBT structure while reduces the leakage current and improves the breakdown voltage. In addition, it enlarges the short circuit safe operating area (SCSOA) of the TAC-IGBT, and is simple in fabrication and design. Simulation results indicate that, for IGBT structures with a breakdown voltage of 1200 V, the leakage current of the new trench gate IGBT structure is one order of magnitude lower than the TAC-IGBT structure and the breakdown voltage is 150 V higher than the TAC-IGBT.

A New Emitter Switched Thyristor (EST) employing Trench Segmented p-base

A new emitter switched thyristor (EST) employing trench segmented p-base, which successfully improves the forward I–V and switching characteristics with decreasing the device active area, is proposed and verified experimentally with using shallow trench process of novel junction termination extension (JTE) method. The latching current of EST is determined by the p-base resistance of upper npn transistor. Floating n+emitter of conventional EST is enlarged to obtain large base resistance. However, the proposed EST increases the p-base resistance with shorter floating n+ emitter than that of conventional one. Shallow trench in floating emitter region forms the highly resistive p-base region under the bottom of trench. The experimental results show that the shortened floating n+ emitter and lowered latching current of proposed EST decrease experimentally the forward voltage drop by 17.7% and snap-back phenomenon with small active area. The breakdown voltage of series lateral MOSFET of proposed EST is increased from 7 to 14V due to the trench filled with oxide which results in vertical redistribution of electric field, therefore current saturation capability and forward biased safe operating area (FBSOA) of proposed EST are enhanced. The simulation results show that the switching operation is performed successfully at the blocking voltage of 600V and Eoff of the proposed one is reduced by 3.7%. The measured inductive load switching characteristics also shows that Eoff of proposed one is improved by 7.2%.

Analysis and optimisation of the trench gated emitter switched thyristor

The performance of the trench gated emitter switched thyristor (TEST) is investigated by numerical simulations. More specifically, the influence of the N+ floating emitter on the forward voltage drop and forward-biased safe operating area (FBSOA) is studied in detail. It is demonstrated that, by reducing the doping of this region, the FBSOA of the TEST can be significantly increased with a negligible degradation of the forward voltage drop VCE(SAT). Moreover, a new cathode design is proposed for the TEST by removing the connection between the two P base regions and leaving one of them floating. By doing so, the snap-back from the static turn-on is removed, and the forward voltage drop is improved even for a lower doping of the N+ floating emitter.

Cascading structure of LDMOS and LIGBT for increasing the forward biased safe operating area

In this paper, a new device structure is proposed to suppress parasitic latch-up effectively and also improve the turn-off characteristic by cascading the drain of lateral double diffused MOSFET (LDMOS) to the cathode of lateral insulated gate bipolar transistor (LIGBT). The forward biased safe operating area of proposed device is large because the parasitic thyristor latch-up is eliminated even in high voltage exceeding 200 V by current saturation of LDMOS. Also switching speed is improved considerably compared with conventional LIGBT. The device characteristics is verified by two-dimensional simulation (MEDICI).

A local charge control technique to improve the forward bias safe operating area of LIGBT

In this paper, for the first time, we demonstrate that incorporation of a shallow, lightly doped floating P -layer in the drift region of a high voltage CMOS/BiCMOS compatible, 500 V lateral insulated gate bipolar transistor can result in a significant improvement of its forward bias safe operating area. Detailed numerical calculations and analysis show that such an approach can enhance the on-state voltage handling capability without decreasing the breakdown voltage. The position of such a layer is shown to have a significant impact on the SOA performance of the device for the parameters considered.

Thermal instability of low voltage power-MOSFETs

This paper analyzes an anomalous failure mechanism detected on last generation low voltage power metal oxide semiconductor (MOS) devices at low drain current. Such a behavior, apparently due to a kind of second breakdown phenomenon, has been scarcely considered in literature, as well as in manufacturer data sheets, although extensive experimental tests show that it is a common feature of modern low voltage metal oxide semiconductor held effect transistor (MOSFET) devices. The paper starts by analyzing some failures, systematically observed on low voltage power MOSFET devices, inside the theoretical forward biased safe operating area. Such failures are then related to an unexpected thermal instability of the considered devices. Experimental tests have shown that in the considered devices the temperature coefficient is positive for a very wide drain current range, also including the maximum value. Such a feature causes hot spot phenomena in the devices, as confirmed by microscope inspection of the failed devices. Finally, it is theoretically demonstrated that the thermal instability is a side effect of the progressive die size and process scaling down. As a result, latest power MOSFETs, albeit more efficient and compact, are less robust than older devices at low drain currents, thus requiring specific circuit design techniques.

Current saturation control in silicon emitter switched thyristors

In this paper a novel Dual Channel Emitter Switched Thyristor (DC-EST) structure with diode diverter connected to the P-base region is shown to provide reduced saturation current density without compromising the on-state voltage drop. During the on-state, the diode diverter does not carry any current and the P-base region is effectively floating in potential, which results in a low on-state voltage drop. During current saturation, as the P-base potential rises, the diode diverter diverts the holes collected in the P-base, thus leading to an improved forward biased safe operating area (FBSOA). The saturation current density is lowered significantly which is desirable to achieve a good short circuit safe operating area (SCSOA). The dynamic clamping behavior of the diode diverter allows for independent optimization of the forward drop and saturation current density. Experimental results are reported to confirm the superior characteristics observed through simulations. The novel diode diverter DC-EST structure is found to be particularly suitable for high voltage (4 kV) applications.

An experimental analysis of the dual gate emitter switched thyristor (DG-EST)

In recent years, various dual MOS gated thyristor structures have been proposed to improve the three pronged trade-off of forward voltage drop, turn-off time and forward biased safe operating area when compared to single gate devices. The dual gate emitter switched thyristor (DG-EST), with its unique thyristor current partitioning mechanism, has been reported to posses superior characteristics when compared to conventional single gate ESTs. In this paper, a detailed study of the device physics of operation of the DG-EST is presented, supported by two dimensional numerical simulations. Effects of variations in the floating emitter length, lifetime in the drift region and temperature on the forward voltage drop are experimentally observed. An analytical model predicting the maximum controllable current density ( J MCC) of the DG-EST is reported and confirmed through experimental measurements. The DG-EST is found to have a superior trade-off curve of on-state voltage drop versus turn-off time when compared to the conventional emitter switched thyristor (C-EST).