For Field Programmable Gate Arrays Research Articles

FPGA‐based hardware‐in‐the‐loop real‐time simulation implementation for high‐speed train electrical traction system

The hardware-in-the-loop (HIL) real-time simulation for high-speed train electrical traction system aims to reduce the design cost and speed up control verification process of algorithms in the developmental stage of the traction control unit. In this study, based on the dSPACE real-time simulator, the multiple-simulator, multiple-simulation step of HIL real-time simulation system is first built. Second, for the associated discrete circuit modelling method, an optimisation method is proposed to minimise the switching loss and improve the simulation accuracy by selecting the optimal discrete-time switch admittance parameter, G S . To decrease the computational burden for field-programmable gate array (FPGA), a decoupling method without simulation latency is presented to reduce the matrix dimension of the system model. Finally, the real-time simulation models of electrical traction system are realised by CPU + FPGA-based simulator, in which the power electronics converter models are computed in FPGA with a fixed 100 ns time-step. The validity and reliability of the real-time simulation system is verified by the HIL simulation and experimental results, which indicate that the real-time HIL simulation at the nanosecond level improves the accuracy essentially.

A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization

A 3.0 GSymbol/s/lane transceiver bridge chip, which fully supports the mobile industry processor interface (MIPI) C-PHY version 1.1 specification, is proposed for field-programmable gate array (FPGA)-based pattern generators and frame grabbers. In transmit mode, it converts parallel low-voltage complementary metal oxide semiconductor (CMOS) signals into high-speed three-level signals when performing serialization. In addition, deserialization including clock recovery from the received data is performed for its receive mode operation. A pre-emphasis transmitter and an elastic receiver that perform equalization according to the signal level are proposed to improve the signal integrity of high-speed three-level signals. The proposed MIPI C-PHY transceiver bridge chip is implemented using a 65 nm CMOS process with 1.2 V supply voltage. The area of each lane is 0.103 mm2 and the power consumption in high-speed transmit and receive modes is 2.96 mW/Gbps/lane and 5.62 mW/Gbps/lane, respectively. The measured peak-to-peak time jitter of the proposed high-speed transmitter, receiver, and clock recovery are 0.27 UI, 0.35 UI, and 90 ps, respectively, at a data rate of 3 GSymbol/s/lane.

An efficient adaptive equalization architecture for high-speed coherent PON systems

Algorithmic and architectural options and tradeoffs between performance and complexity/power dissipation are imperative to be considered in the transfer of coherent technology from long-haul transmission to passive optical network (PON) application. In this work, a novel low-complexity equalization architecture cascaded two frequency domain equalizers (FDEQs) and one 1-tap 2 × 2 butterfly equalizer is proposed targeting PON applications. FDEQ is designed to handle link chromatic dispersion (CD) and the imperfection of transceiver frequency response. The 1-tap 2 × 2 butterfly equalizer is introduced to realize polarization demultiplexing. A simplified FDEQ tap coefficient calculation method is designed. The performance of the proposed equalization architecture is experimentally verified by a 32-GBaud dual-polarization (DP) Nyquist-QPSK system over 20-km standard single-mode fiber (SSMF) transmission. With the proposed method, the number of hardened multipliers for field-programmable gate array (FPGA) realization is reduced by ∼90% compared with conventional 2 × 2 butterfly equalizer, at the expense of 0.5 dB receiver sensitivity.

Hardware Optimized and Error Reduced Approximate Adder

This paper presents a new hardware optimized and error reduced approximate adder (HOERAA), which is suitable for field programmable gate array (FPGA)- and application specific integrated circuit (ASIC)-based implementations. In this work, we consider a FPGA-based implementation using Xilinx Vivado 2018.3, targeting an Artix-7 FPGA. The ASIC-based realizations are based on a 32/28nm complementary metal oxide semiconductor (CMOS) process. Based on FPGA implementations, we note the following: (i) For 32-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 22% fewer look-up tables (LUTs) and 18.6% fewer registers while reducing the minimum clock period by 7.1% and reducing the power-delay product (PDP) by 14.7%, compared to the native accurate FPGA adder, and (ii) for 64-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 11% fewer LUTs and 9.3% fewer registers while reducing the minimum clock period by 8.3% and reducing the PDP by 9.3%, compared to the native accurate FPGA adder. Based on ASIC-style implementations, HOERAA is found to achieve the following reductions in design metrics compared to an optimum accurate carry-lookahead adder: (i) A 15.7% reduction in critical path delay, a 21.4% reduction in area, and a 35% reduction in PDP for 32-bit addition involving a 8-bit least significant inaccurate sub-adder, and (ii) a 15.3% reduction in critical path delay, a 10.7% reduction in area, and a 20% reduction in PDP for 64-bit addition involving a 8-bit least significant inaccurate sub-adder. Moreover, comparisons with other approximate adders show that HOERAA has a significantly reduced average error, mean average error, and root mean square error, while reporting near optimum design metrics.

Fast HUB Floating-Point Adder for FPGA

Several previous publications have shown the area and delay reduction when implementing real number computation using half-unit biased (HUB) formats for both floating-point and fixed-point. In this brief, we present an HUB floating-point adder for field-programmable gate array (FPGA) which greatly improves the speed of previous proposed HUB designs for these devices. Our architecture is based on the double path technique which reduces the execution time since each path works in parallel. We also deal with the implementation of unbiased rounding in the proposed adder. Experimental results are presented showing the goodness of the new HUB adder for FPGA.

A Device-Level Transient Modeling Approach for the FPGA-Based Real-Time Simulation of Power Converters

The device-level real-time simulation of power converters is constrained by the contradiction between the required short simulation time step to describe the transient behaviors and the large computational amount caused by the nonlinearities of switches’ models. In this paper, a novel low-latency device-level power converter modeling approach is proposed for field programmable gate array (FPGA)-based real-time simulation. A piecewise linear insulated-gate bipolar transistor (IGBT)/diode transient model is proposed based on the inductive switching behaviors. The switching transient is modeled into four phases, which are identified by the boundaries between three operating regions of IGBT and between two operating modes of a diode. Moreover, each phase is approximated by a linear continuous behavior in order to reduce the real-time computational amounts. Accompanied by the effective boundary identification, the device-level IGBT/diode model can be efficiently integrated into the real-time simulation with low computational latency. A dc–dc–ac topology model is implemented on the FPGA-based real-time platform, as a case study to verify the effectiveness and practicability of the proposed approach. With the help of circuit partitioning techniques, the device-level converter model can be simulated with a 50-ns time step on FPGA. Moreover, the accuracy of FPGA-based simulation results is validated by the error evaluation with respect to the results from offline simulation tools.

Robust secure communication protocol for smart healthcare system with FPGA implementation

Abstract Vast development of wireless technology and cloud computing has given lots of benefit to the society in a variety of ways. One such application using this technology is telemedicine or mobile healthcare and in this, security is one of the most important concern. In recent times, multimedia applications include mobile networks, integrated sensors and Internet-of-Things (IoT) services. In the landscape of IoT systems, the problem of privacy, security and trust has remained a challenge since several years. There are only few works proposed to support secure communication in the IoT-enabled Medical Wireless Sensor Networks (MWSNs). However, the existing protocols have some design flaws and are vulnerable to several security attacks including sensor and user impersonation attacks. In this paper, a novel architecture in the MWSNs is proposed and a suitable authenticated key establishment protocol using the light weight Elliptic Curve Cryptography (ECC) for the architecture is designed. The proposed authentication protocol solves the security issues found in existing protocols. The formal method Burrows–Abadi–Needham (BAN) logic is enforced to prove the correctness of the protocol. Further investigation has led to the claim that the protocol is safe from known security attacks. In addition, the proposed protocol is described in Verilog Hardware Description Language (HDL) and its functionalities are checked using Altera Quartus II simulation tool for Field-Programmable Gate Array (FPGA) implementation. The analysis of our protocol and comparison of it with similar protocols show that the proposed protocol is more efficient and robust than the existing protocols.

Security of Khudra Against Meet‐in‐the‐Middle‐Type Cryptanalysis

Khudra is a lightweight block cipher proposed in SPACE 2014. The cipher is designed for Field programmable gate array (FPGA) based platforms. In this paper, we introduce the first biclique attack on full Khudra in the single key setting, with time complexity of 278.3 encryptions. The time complexity can be further reduced if the post-whitening key is omitted. Furthermore, based on the bicliques constructed, Meet-in-the-middle(MITM) attack is applied to 15-round Khudra, and the best result of Khudra in terms of attacked rounds against MITM attack is achieved.

Optimized Real-Time Biomimetic Neural Network on FPGA for Bio-hybridization.

Neurological diseases can be studied by performing bio-hybrid experiments using a real-time biomimetic Spiking Neural Network (SNN) platform. The Hodgkin-Huxley model offers a set of equations including biophysical parameters which can serve as a base to represent different classes of neurons and affected cells. Also, connecting the artificial neurons to the biological cells would allow us to understand the effect of the SNN stimulation using different parameters on nerve cells. Thus, designing a real-time SNN could useful for the study of simulations of some part of the brain. Here, we present a different approach to optimize the Hodgkin-Huxley equations adapted for Field Programmable Gate Array (FPGA) implementation. The equations of the conductance have been unified to allow the use of same functions with different parameters for all ionic channels. The low resources and high-speed implementation also include features, such as synaptic noise using the Ornstein–Uhlenbeck process and different synapse receptors including AMPA, GABAa, GABAb, and NMDA receptors. The platform allows real-time modification of the neuron parameters and can output different cortical neuron families like Fast Spiking (FS), Regular Spiking (RS), Intrinsically Bursting (IB), and Low Threshold Spiking (LTS) neurons using a Digital to Analog Converter (DAC). Gaussian distribution of the synaptic noise highlights similarities with the biological noise. Also, cross-correlation between the implementation and the model shows strong correlations, and bifurcation analysis reproduces similar behavior compared to the original Hodgkin-Huxley model. The implementation of one core of calculation uses 3% of resources of the FPGA and computes in real-time 500 neurons with 25,000 synapses and synaptic noise which can be scaled up to 15,000 using all resources. This is the first step toward neuromorphic system which can be used for the simulation of bio-hybridization and for the study of neurological disorders or the advanced research on neuroprosthesis to regain lost function.

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can automatically generate Verilog and SPICE netlists based on realistic FPGA configurations and a high-level eTtensible Markup Language-based FPGA architectural description language. The outputted Verilog netlists can be used to generate layouts of full FPGA fabrics through a semicustom design flow. SPICE simulation decks can be generated at three levels of complexity, namely, full-chip-level, grid-level, and component-level, providing different tradeoff between accuracy and simulation time. In order to enable such level of analysis, we presented two SPICE netlist partitioning techniques: loads extraction and parasitic net activity estimation. Electrical simulations showed that averaged over the selected benchmarks, the grid-/component-level approach can achieve $6.1\times /7.5\times $ execution speed-up with 9.9%/8.3% accuracy loss, respectively, compared to the full-chip level simulation. FPGA-SPICE was showcased through three different case studies: 1) an area breakdown analysis for static random access memory-based FPGAs, showing that configuration memories are a dominant factor; 2) a power breakdown comparison to analytical models, analyzing the source of accuracy loss; and 3) a robustness evaluation against process corners, studying their impact on energy consumption of full FPGA fabrics.

Real-Time Implementation of MAD-Based RFI Excision on FPGA

Radio Frequency Interference (RFI) excision in wideband radio telescope receivers is gaining significance due to increasing levels of manmade RFI and operation outside the protected radio astronomy bands. The effect of RFI on astronomical data can be significantly reduced through real-time excision. In this paper, Median Absolute Deviation (MAD) is used for excising signals corrupted by strong impulsive interference. MAD estimation requires recursive median calculation which is a computationally challenging problem for real-time excision. This challenge is addressed by implementation of a histogram-based technique for MAD computation. The architecture is developed and optimized for Field Programmable Gate Array (FPGA) implementation. The design of a more robust variant of MAD called Median-of-MAD (MoM) is described. The architecture of MAD and MoM techniques and subsequent optimization allows for four RFI excision blocks on a single Xilinx Virtex-5 FPGA. These techniques have been tested on the GMRT wideband backend (GWB) processing a maximum of 400[Formula: see text]MHz bandwidth and the results show significant improvement in the signal-to-noise ratio (SNR).

Field‐programmable gate arrays and quantum Monte Carlo: Power efficient coprocessing for scalable high‐performance computing

AbstractMassively parallel architectures offer the potential to significantly accelerate an application relative to their serial counterparts. However, not all applications exhibit an adequate level of data and/or task parallelism to exploit such platforms. Furthermore, the power consumption associated with these forms of computation renders “scaling out” for exascale levels of performance incompatible with modern sustainable energy policies. In this work, we investigate the potential for field‐programmable gate arrays (FPGAs) to feature in future exascale platforms, and their capacity to improve performance per unit power measurements for the purposes of scientific computing. We have focused our efforts on variational Monte Carlo, and report on the benefits of coprocessing with a FPGA relative to a purely multicore system.

AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation

Binary tree topology generally fails to attract network on chip (NoC) implementations due to its low bisection bandwidth. Fat trees are proposed to alleviate this issue by using increasingly thicker links to connect switches towards the root node. This scheme is very efficient in interconnected networks such as computer networks, which use generic switches for interconnection. In an NoC context, especially for field programmable gate arrays (FPGAs), fat trees require more complex switches as we move higher in the hierarchy. This restricts the maximum clock frequency at which the network operates and offsets the higher bandwidth achieved through using fatter links. In this paper, we discuss the implementation of a binary tree-based NoC, which achieves better bandwidth by varying the clock frequency between the switches as we move higher in the hierarchy. This scheme enables using simpler switch architecture, thus supporting higher maximum frequency of operation. The effect on bandwidth and resource requirement of this architecture is compared with other FPGA-based NoCs for different network sizes and traffic patterns.

Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems

Confronted with the challenge of high performance for applications and the restriction of hardware resources for field-programmable gate arrays (FPGAs), partial dynamic reconfiguration (PDR) technology is anticipated to accelerate the reconfiguration process and alleviate the device shortage. In this paper, we propose an integrated optimization framework for task partitioning, scheduling and floorplanning on partially dynamically reconfigurable FPGAs. The partitions, schedule, and floorplan of the tasks are represented by the partitioned sequence triple P-ST (PS,QS,RS), where (PS,QS) is a hybrid nested sequence pair (HNSP) for representing the spatial and temporal partitions, as well as the floorplan, and RS is the partitioned dynamic configuration order of the tasks. The floorplanning and scheduling of task modules can be computed from the partitioned sequence triple P-ST in O(n^2) time. To integrate the exploration of the scheduling and floorplanning design space, we use a simulated annealing-based search engine and elaborate a perturbation method, where a randomly chosen task module is removed from the partition sequence triple and then inserted back into a proper position selected from all the (n+1)^3 possible combinations of partitions, schedule and floorplan. The experimental results demonstrate the efficiency and effectiveness of the proposed framework.

Support-Reducing Decomposition for FPGA Mapping

Decomposition is a technology-independent process, in which a large complex function is broken into smaller, less complex functions. The costs of two-level or factored-form representations (cubes and literals) are used in most decomposition methods, as they have a high correlation with the area of cell-based designs. However, this correlation is weaker for field-programmable gate arrays (FPGAs) based on look-up tables. Furthermore, local optimizations have limited power due to the structural bias of the circuit descriptions. This paper tries to reduce the structural biasing by remapping the look-up table network and decomposing the derived functions using the support as cost function. The proposed method improves the FPGA mapping results of a commercial tool for the 20 largest MCNC benchmarks, with gains of 28% in delay plus 18% in area when targeting delay, and a reduction of 28% in area plus 14% in delay with area as cost function. Results with 23% less area and 6% less delay are obtained after physical synthesis (post place-and-route). Moreover, 12 of the best known results for delay (and 3 for area) of the EPFL benchmarks are improved.

A CNN Accelerator on FPGA Using Depthwise Separable Convolution

Convolutional neural networks (CNNs) have been widely deployed in the fields of computer vision and pattern recognition because of their high accuracy. However, large convolution operations are computing-intensive that often requires a powerful computing platform such as Graphics Processing Unit (GPU). This makes it difficult to apply CNNs to portable devices. The state-of-the-art CNNs, such as MobileNetV2 and Xception, adopt depthwise separable convolution to replace the standard convolution for embedded platforms. That significantly reduces operations and parameters with only limited loss in accuracy. This highly structured model is very suitable for Field-Programmable Gate Array (FPGA) implementation. In this paper, a scalable high performance depthwise separable convolution optimized CNN accelerator is proposed. The accelerator can be fit into an FPGA of different sizes, provided the balancing between hardware resources and processing speed. As an example, MobileNetV2 is implemented on Arria 10 SoC FPGA, and the results show this accelerator can classify each picture from ImageNet in 3.75ms, which is about 266.6 frames per second. This achieves 20x speedup if compared to CPU.

Code-design for efficient pipelined layered LDPC decoders with bank memory organization

This paper presents an architecture-aware Progressive Edge Growth (PEG)-based construction method for Low-Density Parity-Check (LDPC) codes. We target optimization through code construction for layered architectures with pipelined processing and memory organized in single-port banks. For a given layered Quasy-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture configuration, the code constraints need to maximize hardware usage efficiency. Implementation results for Field-Programmable Gate Array (FPGA) technology suggest that the codes obtained using the proposed algorithm have a throughput increase of 39% up to 110%, due to the increase in working frequency obtained by using pipeline.

Distributed-Memory-Based FFT Architecture and FPGA Implementations

A new class of fast Fourier transform (FFT) architecture, based on the use of distributed memories, is proposed for field-programmable gate arrays (FPGAs). Prominent features are high clock speeds, programmability, reduced look-up-table (LUT) and register usage, simplicity of design, and a capability to do both power-of-two and non-power-of-two FFTs. Higher clock speeds are a consequence of new algorithms and a more fine-grained structure compared to traditional pipelined FFTs, so clock speeds are typically >500 MHz in 65 nm FPGA technology. The programmability derives from the memory-based architecture, which is also scalable. Reduced LUT and register usage arises from a unique methodology to control word growth during computation that achieves high dynamic range, along with inherent systolic circuit characteristics: simple, regular, uniform arrays of processing elements, connected in nearest-neighbor fashion to minimize wiring lengths. The circuit goal was to maximize throughput and minimize the use of the FPGA LUT and register logic fabric. Comparison results from seven different designs, covering a spectrum of functionality (fixed-size, variable, floating-point and variable non-power-of-two FFTs), different FPGA vendors (Intel and Xilinx) and different FPGA types, showed increases in throughput per logic cell up to 181% with an average improvement of 94%.

ASIR: Application-Specific Instruction-Set Router for NoC-Based MPSoCs

The end of Dennard scaling led to the use of heterogeneous multi-processor systems-on-chip (MPSoCs). Heterogeneous MPSoCs provide a high efficiency in terms of energy and performance due to the fact that each processing element can be optimized for an application task. However, the evolution of MPSoCs shows a growing number of processing elements (PEs), which leads to tremendous communication costs, tending to become the performance bottleneck. Networks-on-chip (NoCs) are a promising and scalable intra-chip communication technology for MPSoCs. However, these technological advances require novel and effective programming methodologies to efficiently exploit them. This work presents a novel router architecture called application-specific instruction-set router (ASIR) for field-programmable-gate-arrays (FPGA)-based MPSoCs. It combines data transfers with application-specific processing by adding high-level synthesized processing units to routers of the NoC. The execution of application-specific operations during data exchange between PEs exploits efficiently the transmission time. Furthermore, the processing units can be programmed in C/C++ using high-level synthesis, and accordingly, they can be specifically optimized for an application. This approach enables transferred data to be processed by a processing element, such as a MicroBlaze processor, before the transmission or by a router during the transmission. Moreover, a static mapping algorithm for applications modeled by a Kahn process network-based graph is introduced that maps tasks to the MicroBlaze processors and processing units. The mapping algorithm optimizes the communication cost by allocating tasks to nearest neighboring PEs. This complete methodology significantly simplifies the design and programming of ASIR-based MPSoCs. Furthermore, it efficiently exploits the heterogeneity of processing capabilities inside the routers and MicroBlaze processors.

Fault Tolerance Mechanisms for FPGA-Based Regular Expression Matching

Traditional fault-tolerance techniques relying on spatial and temporal redundancy typically imply high power, delay, and area overheads. Cost-effective solutions often depend on system’s design and hardware platform at hand. Particularly for Field-Programmable Gate Arrays (FPGAs), soft errors on the configuration memory are a significant dependability threat. In this work, we present an extended and comprehensive fault tolerance mechanism especially suited for dealing with configuration faults on FPGA-based systems that must deal multiple failure modes. Each failure mode may present different criticality and probability of occurrence, and these properties are measured and exploited to provide low-cost solutions when compared to standard approaches such as triple modular redundancy. The exploited properties are typically found in critical monitoring systems that may trigger security- or safety-critical alarms and warnings in general. In such systems, failing to trigger an alarm when necessary is frequently regarded as more critical than providing an occasional false alarm. For instance, Regular Expression Matching (REM), a compute-intensive mechanism heavily used to perform Deep Packet Inspection in critical network applications, presents such properties, and it can be greatly accelerated by FPGAs to meet performance constraints in high-throughput networks. Therefore, we use FPGA-based REM engines as a case study to demonstrate the effectiveness of the proposed techniques. Additionally, a mutually-aware placement and scrubbing mechanism is introduced to reduce the repair time, improving the system reliability and availability. Experimental results show that the failure rate and the repair time can be reduced by 95 and 90% respectively while avoiding the costs of triplication.