Abstract
In this paper, a fast Fourier transform (FFT) hardware architecture optimized for field-programmable gate-arrays (FPGAs) is proposed. We refer to this as the single-stream FPGA-optimized feedforward (SFF) architecture. By using a stage that trades adders for shift registers as compared with the single-path delay feedback (SDF) architecture the efficient implementation of short shift registers in Xilinx FPGAs can be exploited. Moreover, this stage can be combined with ordinary or optimized SDF stages such that adders are only traded for shift registers when beneficial. The resulting structures are well-suited for FPGA implementation, especially when efficient implementation of short shift registers is available. This holds for at least contemporary Xilinx FPGAs. The results show that the proposed architectures improve on the current state of the art.
Highlights
Hardware implementations of cores for computation of the discrete Fourier transform (DFT) continuously find more applications
The results show that the proposed architectures are well-suited for field-programmable gate-arrays (FPGAs) implementation, at least in FPGAs where short shift registers can be efficiently implemented, such as contemporary Xilinx FPGAs
stream FPGA-optimized feedforward (SFF), a new single-stream pipeline fast Fourier transform (FFT) architecture is proposed. It is well suited for implementation in FPGAs with efficient shift register implementation, which at least includes contemporary Xilinx FPGAs
Summary
Hardware implementations of cores for computation of the discrete Fourier transform (DFT) continuously find more applications. This was to some degree shown in [15, 16], where transformations allowing a better FPGA-mapping of radix-2 SDF pipeline FFTs were proposed. A new single-stream radix-2 pipeline FFT architecture is proposed. We refer to this architecture as the single-stream FPGA-optimized feedforward (SFF) architecture. The results show that the proposed architectures are well-suited for FPGA implementation, at least in FPGAs where short shift registers can be efficiently implemented, such as contemporary Xilinx FPGAs. The paper is organized as follows: in Section 2, the SFF and SFF/SDF architectures are described.
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