For Field Programmable Gate Arrays Research Articles

Feed Forward Neural Network With Column-Wise Matrix–Vector Multiplication on FPGAs

This article presents a reconfigurable accelerator for recurrent neural networks with fine grained column wise matrix vector multiplication (RENOWN).We propose a novel latency hiding architecture for recurrent neural network accelerator using column wise matrix vector multiplication instead of the state of the art row wise operation. This hardware (HW) architecture can eliminate data dependencies to improve the throughput of RNN inference systems. Besides, we introduce a configurable checkerboard tiling strategy which allows large weight matrices, while incorporating various configurations of element-based parallelism (EP) and vector-based parallelism (VP). These optimizations improve the exploitation of parallelism to increase HW utilization and enhance system throughput. Evaluation results show that our design can achieve over 29.6 tera operations per second (TOPS) which would be among the highest for field-programmable gate array (FPGA)-based RNN designs. Compared to state-of-the-art accelerators on FPGAs, our design achieves 3.7–14.8 times better performance and has the highest HW.

Energy efficient FPGA implementation of an epileptic seizure detection system using a QDA classifier

Epilepsy is a severe neurological disorder that causes seizures. It is detected by analyzing the electrical impulses of the human brain. Monitoring the brain is commonly done using an electroencephalogram (EEG). Seizure detection from the large recorded EEG dataset is a demanding task. However, numerous machine learning classifiers and the appropriate features can detect seizures. The Hjorth and statistical parameters are used in this study to provide an effective method for field programmable gate array (FPGA) realization of epileptic seizure detectors from EEG signals. Mobility, interquartile range (IQR), median absolute deviation (MAD), energy, non-linear energy, and simple square integral (SSI) are the various features analyzed in this work. The hardware architecture of the seizure detection system is captured in Verilog hardware descriptive language and realized on the Artix-7 FPGA. This paper presents three separate seizure detection models designed by pairing three different features with the Quadratic discriminant analysis (QDA) classifier. Among these three models, the energy and non-linear energy-based seizure detection system offers better performance than existing seizure detection systems because it possesses the lowest dynamic power consumption (0.116 µW), the highest design accuracy (99.4 %), and the highest sensitivity (100 %), which makes it the best seizure detection system for real-time applications.

Enhancing High-Speed Data Transfer in Fpga-Based Systems: An Innovative Usb 3.0 Communication Interface Design

This study introduces an innovative design for a USB 3.0 communication interface, specifically tailored for Field-Programmable Gate Arrays (FPGAs). Given the escalating requirements for rapid data transmission in contemporary computer applications, USB 3.0 provides substantial enhancements over its antecedents. Nonetheless, extant USB communication interfaces inadequately cater to FPGA development, leading to diminished productivity for developers. To reconcile this discrepancy, this paper advocate for an Intellectual Property (IP) core interface that capitalizes on the concurrent data transmission proficiency of FPGAs, in conjunction with the superior speed transfer of USB 3.0. This design employs the CYUSB3014 chip, amalgamating the Physical Layer (PHY), Serial Interface Engine (SIE), and driver software into a singular entity. Herein, the FPGA serves as the nexus of control, streamlining data interchange and interface coordination among diverse modules within the system. The design put forth not only enables expeditious data communication in FPGA-centric systems, thereby surmounting the constraints of conventional USB interfaces, but also promotes accelerated data conveyance and augmented development efficiency. Consequently, this design harbors extensive applicability across spheres of digital system design and communications.

Highly optimized quantum circuits synthesized via data-flow engines

The formulation of quantum programs in terms of the fewest number of gate operations is crucial to retrieve meaningful results from the noisy quantum processors accessible these days. In this work, we demonstrate a use-case for Field Programmable Gate Array (FPGA) based data-flow engines (DFEs) to scale up variational quantum compilers to synthesize circuits up to 9-qubit programs. This gate decomposer utilizes a newly developed DFE quantum computer simulator that is designed to simulate arbitrary quantum circuit consisting of single qubit rotations and controlled two-qubit gates on FPGA chips. In our benchmark with the QISKIT package, the depth of the circuits produced by the SQUANDER package (with the DFE accelerator support) were less by 97% on average, while the fidelity of the circuits was still close to unity up to an error of ∼10−4.

A Scalable Spatial–Temporal Correlated Non-Stationary Channel Fading Generation Method

To address the challenges of complex implementation structures and high hardware resource consumption in multiple-input multiple-output (MIMO) channel emulators, this paper proposes a hardware generation method for spatial–temporal correlated non-stationary channel fading. Firstly, a hardware generation architecture is developed for field-programmable gate array (FPGA) platforms, which can also reduce the complexity of the channel emulator. Secondly, an improved CORDIC method is introduced to reduce algorithm latency and hardware consumption while expanding the function convergence domain, with a relative error maintained at the level of 10-4. Furthermore, based on the idea of time-division multiplexing, an efficient hardware operation of a lower triangular matrix is adopted to minimize the consumption of hardware resources. Finally, the measured results demonstrate that the statistical characteristics of the channel fading generated by the proposed method are in good agreement with the theoretical ones, with an average error of less than 2%. Additionally, under identical simulation conditions, hardware resource consumption is reduced by 6.87%. These findings provide compelling evidence of the enhanced efficiency and accuracy in simulating MIMO channels achieved through the proposed method.

FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization

Spiking neural networks (SNNs) have been widely used due to their strong biological interpretability and high energy efficiency. With the introduction of the backpropagation algorithm and surrogate gradient, the structure of spiking neural networks has become more complex, and the performance gap with artificial neural networks has gradually decreased. However, most SNN hardware implementations for field-programmable gate arrays (FPGAs) cannot meet arithmetic or memory efficiency requirements, which significantly restricts the development of SNNs. They do not delve into the arithmetic operations between the binary spikes and synaptic weights or assume unlimited on-chip RAM resources by using overly expensive devices on small tasks. To improve arithmetic efficiency, we analyze the neural dynamics of spiking neurons, generalize the SNN arithmetic operation to the multiplex-accumulate operation, and propose a high-performance implementation of such operation by utilizing the DSP48E2 hard block in Xilinx Ultrascale FPGAs. To improve memory efficiency, we design a memory system to enable efficient synaptic weights and membrane voltage memory access with reasonable on-chip RAM consumption. Combining the above two improvements, we propose an FPGA accelerator that can process spikes generated by the firing neuron on-the-fly (FireFly). FireFly is the first SNN accelerator that incorporates DSP optimization techniques into SNN synaptic operations. FireFly is implemented on several FPGA edge devices with limited resources but still guarantees a peak performance of 5.53TOP/s at 300MHz. As a lightweight accelerator, FireFly achieves the highest computational density efficiency compared with existing research using large FPGA devices.

Area & power modeling for different tree topologies of parallel prefix adders

Parallel prefix adder (PPA) being an indispensable component of processors needs prompt estimation of design metrics at the initial stage of design cycle. However, the available commercial tools take significant amount of time for the estimation process. The prior availability of area and power models can greatly reduce time-to-market. Symmetrical construction and quick computational ability of PPAs make them competent candidates for adder circuits in complex applications. This paper proposes area and power models for Field Programmable Gate Arrays (FPGA) implementation of classic PPAs, targeted to Xilinx Zynq-7000 family. The available literature barely presents parameters estimation and their analysis for PPAs. Therefore, modeling proposed in this paper is a novel work. PPA structures are simulated, synthesized and implemented using commercial tool i.e. VIVADO IDE. Models have been developed using curve fitting and validated against commercial tool. Results show an average estimation error ranging from 0.37% to 1.34% in case of area modeling and 0.23% to 0.59% in case of power modeling which are comparable with state of the art.

A New Recursive Trigonometric Technique for FPGA-Design Implementation

This paper presents a new recursive trigonometric (RT) technique for Field-Programmable Gate Array (FPGA) design implementation. The traditional implementation of trigonometric functions on FPGAs requires a significant amount of data storage space to store numerous reference values in the lookup tables. Although the coordinate rotation digital computer (CORDIC) can reduce the required FPGA storage space, their implementation process can be very complex and time-consuming. The proposed RT technique aims to provide a new approach for generating trigonometric functions to improve communication accuracy and reduce response time in the FPGA. This new RT technique is based on the trigonometric transformation; the output is calculated directly from the input values, so its accuracy depends only on the accuracy of the inputs. The RT technique can prevent complex iterative calculations and reduce the computational errors caused by the scale factor K in the CORDIC. Its effectiveness in generating highly accurate cosine waveform is verified by simulation tests undertaken on an FPGA.

A Comprehensive Memory Management Framework for CPU-FPGA Heterogenous SoCs

Efficient utilization of restrained memory resources is of paramount importance in CPU-FPGA heterogeneous multiprocessor system-on-chip (HMPSoC)-based system design for memory-intensive applications. State-of-the-art high level synthesis (HLS) tools rely on the system programmers to manually determine the data placement within the complex memory hierarchy. Different data placement policies may lead to different system performance, and finding an optimal data placement policy is a nontrivial problem. For instance, we show counter-intuitive results that traditional frequency and locality-based data placement strategy designed for CPU architecture leads to nonoptimal system performance in CPU-FPGA HMPSoCs. In this work, we first propose an automatic data placement framework for field programmable gate array (FPGA) kernels to determine whether each array object should be accessed via the on-chip BRAM, shared CPU L2-cache, or DDR memory to achieve the optimal performance. Moreover, we find that when the CPU kernel and the FPGA kernel are executed in parallel, memory contentions may degrade the performance and the optimal data placement policy designed for the FPGA kernel alone will not achieve the optimal overall system performance. In this article, we proposed to use cache partitioning to alleviate the impact brought by memory contentions. We extend the framework designed for FPGA by adding the cross-layer memory contentions analysis to automatically generate an optimal data placement policy and cache partitioning mechanism for the parallel executing kernels. The proposed data placement framework can be seamlessly integrated with the commercial Vivado HLS. The experimental results on the Zedboard platform show an average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times $ </tex-math></inline-formula> performance speedup for FPGA kernels compared with a greedy-based allocation strategy. When FPGA kernels and CPU kernels are executed in parallel, the FPGA kernel and the CPU kernel have a performance speedup of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.62\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.10\times $ </tex-math></inline-formula> on average, respectively.

Design of novel high speed parallel prefix adder

Adders are crucial logical building blocks found almost in all the modern electronic system designs. In the adder architecture design, the fundamental issue is the propagation latency in the carry chain. As the length of the input operands increases, the length of the carry chain along with it. Parallel prefix adders, which address the problem of carry propagation in adders, are the most efficient adder topologies for hardware implementation. However, delay reduction still could be achieved for very high speed applications. Hence, in this paper design of 16bit novel parallel prefix adder is proposed and compared against the existing parallel prefix adder architectures. The design and simulation are carried out using xilinx vivado for field- programmable gate array (FPGA) simulation and Cadence® for ASIC. The results of ASIC implementation demonstrate 17.8% delay reduction while compared to sparse kogge-stone adder.

RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency

The rapid updates in error-resilient applications along with their quest for high throughput have motivated designing fast approximate functional units for Field-Programmable Gate Arrays (FPGAs). Studies that proposed imprecise functional techniques are posed with three shortcomings: first, most inexact multipliers and dividers are specialized for Application-Specific Integrated Circuit (ASIC) platforms. Second, state-of-the-art (SoA) approximate units are substituted, mostly in a single kernel of a multi-kernel application. Moreover, the end-to-end assessment is adopted on the Quality of Results (QoR), but not on the overall gained performance. Finally, existing imprecise components are not designed to support a pipelined approach, which could boost the operating frequency/throughput of, e.g., division-included applications. In this paper, we propose RAPID, the first pipelined approximate multiplier and divider architecture, customized for FPGAs. The proposed units efficiently utilize 6-input Look-up Tables (6-LUTs) and fast carry chains to implement Mitchell's approximate algorithms. Our novel error-refinement scheme not only has negligible overhead over the baseline Mitchell's approach but also boosts its accuracy to 99.4% for arbitrary size of multiplication and division. Experimental results demonstrate the efficiency of the proposed pipelined and non-pipelined RAPID multipliers and dividers over accurate counterparts. Moreover, the end-to-end evaluations of RAPID, deployed in three multi-kernel applications in the domains of bio-signal processing, image processing, and moving object tracking for Unmanned Air Vehicles (UAV) indicate up to 45% improvements in area, latency, and Area-Delay-Product (ADP), respectively, over accurate kernels, with negligible loss in QoR.

Automatic diagnostic system for segmentation of 3D/2D brain MRI images based on a hardware architecture

Magnetic resonance imaging is among the advanced diagnostic testing tools for brain health issues. This method captures a series of detailed head images. These images are then printed and diagnosed by a specialist doctor to demonstrate differences in the brain tissue. Accordingly, additional diagnostic information can be given to determine the extent of the damage and the appropriate treatment methods. In this paper, and in order to facilitate the work of the specialist doctor and help him, we propose an automated hardware architecture for 3D/2D segmentation on MRI images to diagnose differences in brain tissue. For this, we used the metaheuristic technique based on Particle Swarm Optimization (PSO); for which we proposed improvements both for the velocity and position equations and for the fitness function. The goal of the work is to develop a real time automatic system for MRI images segmentation with improved metrics such as accuracy, sensitivity, specificity, dice metrics, execution time and resources utilization. The proposed hardware architecture was synthetized and then co-simulated using Matlab-Vivado System (VSM) for Field Programmable Gate Array (FPGA). Results show that our 3D segmentation method benefited from 2D segmentation with 95.39% accuracy rate and 87.97% DSC similarity (for 5-level segmentation) with 4.57 ms execution time for the case of BraTS 2013 dataset of brain MRI Images.

Infrared Image Pre-Processing and IR/RGB Registration with FPGA Implementation

Infrared imaging sensors are frequently used in thermal signature detection applications in industrial, automotive, military and many other areas. However, advanced infrared detectors are generally associated with high costs and complexity. Infrared detectors usually necessitate a thermoelectric heater–cooler for temperature stabilization and various computationally complex preprocessing algorithms for fixed pattern noise (FPN) correction. In this paper, we leverage the benefits of uncooled focal plane arrays and describe a complete digital circuit design for Field Programmable Gate Array (FPGA)-based infrared image acquisition and pre-processing. The proposed design comprises temperature compensation, non-uniformity correction, defective pixel correction cores, spatial image transformation and registration with RGB images. When implemented on Xilinx Ultrascale+ FPGA, the system achieves a throughput of 30 frames per second using the Fraunhofer IMS Digital 17 μm QVGA-IRFPA with a microbolometer array size of 320 × 240 pixels and an RGB camera with a 1024 × 720 resolution. The maximum ratio of the standard deviation to the mean of 0.35% was achieved after FPN correction.

An SSD-MobileNet Acceleration Strategy for FPGAs Based on Network Compression and Subgraph Fusion

Over the last decade, various deep neural network models have achieved great success in image recognition and classification tasks. The vast majority of high-performing deep neural network models have a huge number of parameters and often require sacrificing performance and accuracy when they are deployed on mobile devices with limited area and power consumption. To address this problem, we present an SSD-MobileNet-v1 acceleration method based on network compression and subgraph fusion for Field-Programmable Gate Arrays (FPGAs). Firstly, a regularized pruning algorithm based on sensitivity analysis and Filter Pruning via Geometric Median (FPGM) was proposed. Secondly, the Quantize Aware Training (QAT)-based network full quantization algorithm was designed. Finally, a strategy for computing subgraph fusion is proposed for FPGAs to achieve continuous scheduling of Programmable Logic (PL) operators. The experimental results show that using the proposed acceleration strategy can reduce the number of model parameters by a factor of 11 and increase the inference speed on the FPGA platform by a factor of 9–10. The acceleration algorithm is applicable to various mobile edge devices and can be applied to the real-time monitoring of forest fires to improve the intelligence of forest fire detection.

Touch-Programmable Metasurface for Various Electromagnetic Manipulations and Encryptions.

Previous programmable metasurfaces integrated with diodes or varactors require external instructions for field programmable gate arrays (FPGAs), which usually rely on computer-inputs or pre-loaded algorithms. But the complicated external devices make the coding regulation process of the programmable metasurfaces cumbersome and difficult to use. To simplify the process and provide a new interaction manner, a touch-programmable metasurface (TPM) based on touch sensing modules is proposed to realize various electromagnetic (EM) manipulations and encryptions. By simply touching the meta-units of the TPM, the state of the diodes can be changed. Through the touch controls, the TPM can achieve independent and direct manipulations of meta-units and efficient inputs of coding patterns without using a FPGA or other control modules. Various coding patterns are demonstrated to achieve diverse scattering-field control and flexible near-field EM information encryptions, which verifies the feasibility of the TPM design. The presented TPM will have wide application prospects in imaging displays, wireless communications, and EM information encryptions.

A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation Scheme

A novel ring oscillator-based Vernier-type time interpolation method, known as the fine-timestamp maker, is proposed for field programmable gate array (FPGA)-based time-to-digital converters (TDCs). This method determines lower measurement dead time and improves resolution by using a bi-time interpolation scheme, first presented in this paper. Additionally, a group of cascaded delay units are packaged as an intellectual property core (DU-IP) to form a ring delay line and to adjust its length via the engineering change order (ECO) tool, which makes the adjustment of the ring oscillator’s frequency more linear and less position dependent. A prototype TDC was implemented on a Kintex-7 FPGA. The experimental results demonstrate that a single TDC channel only consumes 35 DFFs, 31 LUTs, and 16 CARRY4 logics after specific adjustment. The results, with a time resolution of 20 ps, dead time of 58 ns, and a root-mean-square error of 15–20 ps, show a significant performance improvement compared to traditional Vernier-type TDCs.

NTT Architecture for a Linux-Ready RISC-V Fully-Homomorphic Encryption Accelerator

This paper proposes two architectures for the acceleration of Number Theoretic Transforms (NTTs) using a novel Montgomery-based butterfly. We first design a custom NTT hardware accelerator for Field-Programmable Gate Arrays (FPGAs). The butterfly architecture is expanded to a Modular Arithmetic Logic Unit (MALU) and for greater reuse and easier programmability a six-stage pipeline Linux-ready RISC-V core is extended with custom instructions. The performance of the proposed architectures is assessed on a Xilinx Ultrascale+ FPGA and with an Application-Specific Integrated Circuit (ASIC) on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$28{n}\text{m}$ </tex-math></inline-formula> CMOS technology. In FPGA, the results for custom acceleration show reductions of 30%, 90% and 42% in the number of Lookup tables (LUTs) and registers, Block RAMs (BRAMs) and Digital Signal Processors (DSPs), while providing a speedup of 1.9 times, in comparison with the state of the art. The ASIC results show that at 1 GHz the proposed architecture is in average 45% and 52% less area and power hungry, respectively, compared to the state of the art. Furthermore, the proposed MALU, operating as an additional execution unit, increases the overall area of the extended RISC-V core by only 10%, without significant changes in the frequency of operation.

Neuromorphic solutions: digital implementation of bio-inspired spiking neural network for electrocardiogram classification

Conventional techniques of off-chip processing for wearable devices cause high hardware resource usage which leads to heat generation and increased power consumption. &lt;span&gt;Hence, edge computing methods such as neuromorphic computing are considered the most promising modern technology to replace conventional processing. It is beneficial to employ neuromorphic processing in electrocardiogram (ECG) classification, enabling engineers to overcome the constraints of heat generation caused by hardware utilization. Thus, this work aims to investigate common building blocks in a spiking neural network (SNN), analyze the spike-based plasticity mechanism and implement ECG classification on a neuromorphic circuit. The MIT-BIH Arrhythmia database (MITDB) is preprocessed in MATLAB, then used to train and test an SNN designed for field programmable gate arrays (FPGA), employing spike-based plasticity and Izhikevich neurons. The behaviour of spike timing dependent plasticity (STDP) in a neuromorphic circuit is also visualized in this work. The state-of the-art performance of this work lies in providing a generic mechanism to adapt ECG classification into a neuromorphic solution, a non-Von Neumann architecture. The proposed digital design utilizes 1.058% of hardware resources on a Zedboard. Application-wise, this work provides a foundation for development of neuromorphic computing in wearable medical devices that perform continuous monitoring of ECG&lt;/span&gt;.

Low energy non-volatile look-up table using 2 bit ReRAM for field programmable gate array

A low energy non-volatile look-up table (NV-LUT) consisting of 2 bit resistive random-access memories (2 bit ReRAMs) for field-programmable gate arrays (FPGAs) is investigated in this paper. The multi-bit (MB) LUT configuration reduces the number of array cells by half compared to single-bit (SB) ReRAM-based arrays. A comparison of WRITE and READ delay time, energy consumption, and energy delay product (EDP) is carried out between the SB-NVLUT and MB-NVLUT. Different 2, 4, 6, and 8-input LUT configurations were compared. For WRITE 0 and 1 conditions, the MB-NVLUT is 2× faster than the SB-NVLUT and has an average of 1.22× and 2× lower energy consumption and 2.46× and 4.6× lower EDP respectively. For 01 → 10 switching, the MB-NVLUT write delay remains 2× quicker while having 1.03× lower energy consumption and 2.05× lower EDP. The MB-NVLUT is 9.2× lower in write delay, 128× lower in energy consumption, and 153× lower in EDP compared to the SB-NVLUT in 10 → 01 switching. SB-NVLUTs and MB-NVLUTs are then evaluated on Virtex 4 and Virtex 5 FPGA benchmark circuits with the average EDP for SB-NVLUTs greater than that of the MB-NVLUTs and both NVLUTs demonstrating performance matching conventional static RAM LUTs. A LUT controller circuit specifically designed for MB-NVLUT arrays is proposed. The reduction in the MB-NVLUT array cells leads to reduction in components in the controller circuit and improved performances over SB-NVLUTs.

Graph Neural Networks for Charged Particle Tracking on FPGAs.

The determination of charged particle trajectories in collisions at the CERN Large Hadron Collider (LHC) is an important but challenging problem, especially in the high interaction density conditions expected during the future high-luminosity phase of the LHC (HL-LHC). Graph neural networks (GNNs) are a type of geometric deep learning algorithm that has successfully been applied to this task by embedding tracker data as a graph—nodes represent hits, while edges represent possible track segments—and classifying the edges as true or fake track segments. However, their study in hardware- or software-based trigger applications has been limited due to their large computational cost. In this paper, we introduce an automated translation workflow, integrated into a broader tool called hls4ml, for converting GNNs into firmware for field-programmable gate arrays (FPGAs). We use this translation tool to implement GNNs for charged particle tracking, trained using the TrackML challenge dataset, on FPGAs with designs targeting different graph sizes, task complexites, and latency/throughput requirements. This work could enable the inclusion of charged particle tracking GNNs at the trigger level for HL-LHC experiments.