Circuit Footprint Research Articles

Miniaturized IPD-based bandpass filter chip with edge self-coupled SRR and mixed coupling structure for 5G new radio

ABSTRACT A miniaturised millimetre-wave bandpass filter chip based on the integrated passive device (IPD) process for 5 G new radio is proposed in this paper. Two techniques are utilised to minimise the circuit footprint. Firstly, the innovative edge self-coupled split ring resonator (ES-SRR) is proposed, which incorporates a self-coupled effect by narrowing the gap between the vertical microstrip line and the two split stubs. The theoretical model of the ES-SRR is examined to identify its resonating characteristics. Secondly, the magnetic dominant mixed-coupling structure is implemented in the planar filter by meticulously adjusting the resonator line widths. This configuration generates two transmission zeros at each side of the passband. To demonstrate their effectiveness, a sixth-order bandpass filter, operating within the frequency range of 24.25–29.5 GHz, is simulated and fabricated using 100-µm-thick GaAs IPD technology. Experimental results reveal an insertion loss of 2.95 dB and a minimum return loss of 17 dB, achieving a fractional bandwidth of 21%. Notably, the filter exhibits two transmission zeros at 21 GHz and 33 GHz with rejection levels of 55 dB and 60 dB, respectively.

Mixed volatility in a single device: memristive non-volatile and threshold switching in SmNiO3/BaTiO3 devices

Analog neuromorphic circuits use a range of volatile and non-volatile memristive effects to mimic the functionalities of neurons and synapses. Creating devices with combined effects is important for reducing the footprint and power consumption of neuromorphic circuits. This work presents an epitaxial SmNiO3/BaTiO3 electrical device that displays non-volatile memristive switching to either allow or block access to a volatile threshold switching regime. This behavior arises from coupling the BaTiO3 ferroelectric polarization to SmNiO3 metal–insulator transition; the polarization in the BaTiO3 layer that is in contact with the SmNiO3 layer modifies the device resistance continuously in a controllable, non-volatile manner. Additionally, the polarization state varies the threshold voltage at which the Joule-heating-driven insulator-to-metal phase transition occurs in the nickelate, which results in a negative differential resistance curve and produces a sharp, volatile threshold switch. Reliable current oscillations with stable frequencies, large amplitude, and a relatively low driving voltage are demonstrated when the device is placed in a Pearson–Anson-like circuit.

Design, refinement, and enhancement of FPGA-implemented UART circuitry

This article provides an overview of the universal asynchronous receiver/transmitter, commonly referred to as Universal Asynchronous Receiver/Transmitter (UART). The UART stands as a noteworthy exemplar of a serial communication protocol, facilitating the exchange of data within a serial connection while accommodating full-duplex communication. The architecture of the UART hinges upon three principal constituents: the transmitter, the receiver, and the baud rate generator, the latter essentially a frequency divider. Each of these elements is meticulously crafted using the Verilog hardware description language, thereby ensuring distinct and efficient design. Furthermore, this discourse delves into refined iterations of these implementations. For instance, it introduces the concept of a baud rate self-adaptive function and expounds upon multibyte transmission techniques. In a concerted effort to streamline circuit design and curtail the electro circuit's footprint, a deliberate decision is made to forgo the integration of a parity check module. Consequently, the chosen data format is the widely adopted 8N1 (8 data bits, 1 stop bit and no parity bit) configuration.

Highly Reconfigurable Logic‐In‐Memory Operations in Tunable Gaussian Transistors for Multifunctional Image Processing

AbstractReconfigurable logic‐in‐memory device, albeit a promising hardware platform for constructing parallel computing architectures, still suffers from high power‐consumption and low area‐efficiency arising from the circuit redundancy in silicon (Si) based technical path. 2D materials are identified as potential building blocks to significantly reduce the circuit footprints with outstanding power‐efficiency, owing to their atomically thin nature and unique electronic properties. However, the present 2D logic devices are primarily based on single channel materials with homogeneous transport polarities, limiting the device reconfigurability for multi‐functional applications. Here, 2D p–n junction based dual‐gate Gaussian‐type transistors for simplified reconfigurable logic circuits are reported. All fundamental Boolean logic operators are implemented in a single device with electrically driven reconfigurability, giving rise to an ultra‐low transistor consumption down to 13% of the traditional circuits. The device is also demonstrated as a reliable image processing unit for various computing tasks (pixel processing, comparing, and ciphering) by executing the corresponding logic operations. Moreover, in situ memory of the Boolean logics is achieved by engineering the dielectric properties of the transistor without compromising its reconfigurability. These findings provide a potential approach to achieving reconfigurable logic‐in‐memory operations at the hardware level, with significant implications for the advancement of parallel computing.

Design of a Bandpass Filter with Mixed Electromagnetic Coupling Paths Using Vertical Split-Ring Resonators

We propose bandpass filters (BPFs) with mixed electromagnetic coupling paths (MEMCPs) that comprise two coupled vertical split-ring resonators (VSRRs) and present the equivalent circuit models of the coupled VSRRs. We demonstrate that the dominant coupling modes for the top and bottom layers of the VSRRs are magnetic (M) and electric (E), respectively, and that M-dominant coupling is required for high-selectivity BPFs. BPFs with narrow and wide bandwidths were designed based on the generalized coupling matrix. The proposed BPFs were fabricated and measured, and it is verified that the proposed BPFs have high selectivity due to the transmission zeros and a small circuit footprint due to the vertical structure of resonators. The fabricated narrow- and wide-band BPFs have the fractional bandwidths of 3.62% and 5.81%, respectively, with the overall size of 0.29 λ g × 0.043 λ g .

Design of Efficient AI Accelerator Building Blocks in Quantum-Dot Cellular Automata (QCA)

Digital circuit design technologies based on Quantum-Dot Cellular Automata (QCA) have many advantages over CMOS, such as higher intrinsic switching speed up to Terahertz, lower power consumption, smaller circuit footprint, and higher throughput due to compatibility of the inherent signal propagation scheme with pipelining. Hence, QCA is a perfect candidate to provide a circuit design framework for applications such as Artificial Intelligence (AI) accelerators, where real-time energy-efficient performance needs to be delivered at low cost. A novel QCA design approach based on optimal mix of Majority and NAND-NOR-INVERTER (NNI) gates with USE (Universal, Scalable, Efficient) clocking scheme, has been investigated in this work for latency and energy consumption improvements to fundamental building blocks in AI-accelerators, including multipliers, adders, accumulators and SRAMs. The common <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times 4$ </tex-math></inline-formula> Vedic multiplier has been redesigned using the proposed approach, and simulated to yield 62.8% reduction in cell count, 82.2% reduction in area, and 71.2% reduction in latency. 83% reduction in cell count, 94.5% reduction in area, and 94.6% reduction in latency was simulated for the proposed 8-bit PIPO register. The proposed SRAM cell design is estimated to have similar improvement figures to those achieved by the sub-blocks, such as the D-Latch, which has been simulated to exhibit 44.4% reduction in cell count, 50% reduction in both area and latency, and 73% reduction in energy dissipation. The contributions from this work can be directly applied to low cost, high throughput, energy efficient AI-accelerators that can potentially deliver orders of magnitude better energy-delay characteristics than their CMOS counterparts, and significantly better energy-delay characteristics than state-of-the-art QCA implementations.

Stripline Multilayer Devices Based on Complementary Split Ring Resonators.

A new analytic design for multilayer stripline devices in planar circuit technology is presented. The Complementary Split Ring Resonator (CSRR) is used as a sub-wavelength resonant particle, which provides high-Q resonances in a compact size. The electromagnetic field distribution achieved along the stripline enables enhanced excitation of the resonators. An optimal solution for multilayer power dividers is presented, in a configuration in which each output is obtained in different layers and also in a different layer than the input line. The solution is expanded to design different devices, such as diplexers, resonators, and multi-frequency resonators, leading to vertical filters. As the resonances are achieved by stacking resonators, the effective circuit footprint is very compact. The proposed devices can be implemented in a volumetric chip fashion, allowing integration with planar transmission line circuits and flexible output connection placement. A complete analysis of the different devices is proposed, extracting and verifying their equivalent circuit models.

Multi-functional multi-gate one-transistor process-in-memory electronics with foundry processing and footprint reduction

Logic gates are fundamental components of integrated circuits, and integration strategies involving multiple logic gates and advanced materials have been developed to meet the development requirements of high-density integrated circuits. However, these strategies are still far from being widely applicable owing to their incompatibility with the modern silicon-based foundry lines. Here, we propose a silicon-foundry-line-based multi-gate one-transistor design to simplify the conventional multi-transistor logic gates into one-transistor gates, thus reducing the circuit footprint by at least 40%. More importantly, the proposed configuration could simultaneously provide the multi-functionalities of logic gates, memory, and artificial synapses. In particular, our design could mimic the artificial synapses in three dimensions while simultaneously being implemented by standard silicon-on-insulator process technology. The foundry-line-compatible one-transistor design has great potential for immediate and widespread applications in next-generation multifunctional electronics.

Non-Volatile Programmable Ultra-Small Photonic Arbitrary Power Splitters.

A series of reconfigurable compact photonic arbitrary power splitters are proposed based on the hybrid structure of silicon and Ge2Sb2Se4Te1 (GSST), which is a new kind of non-volatile optical phase change material (O-PCM) with low absorption. Our pixelated meta-hybrid has an extremely small photonic integrated circuit (PIC) footprint with a size comparable to that of the most advanced electronic integrated circuits (EICs). The power-split ratio can be reconfigured in a completely digital manner through the amorphous and crystalline switching of the GSST material, which only coated less than one-fifth of the pattern allocation area. The target power–split ratio between the output channels can be arbitrarily reconfigured digitally with high precision and in the valuable C-band (1530–1560 nm) based on the analysis of three-dimensional finite-difference time-domain. The 1 × 2, 1 × 3, and 1 × 4 splitting configurations were all investigated with a variety of power–split ratios for each case, and the corresponding true value tables of GSST distribution are given. These non-volatile hybrid photonic splitters offer the advantages of an extremely small footprint and non-volatile digital programmability, which are favorable to the truly optoelectronic fusion chip.

Constrained multi-objective optimization of compact microwave circuits by design triangulation and pareto front interpolation

Development of microwave components is an inherently multi-objective task. This is especially pertinent to the design closure stage, i.e., final adjustment of geometry and/or material parameters carried out to improve the electrical performance of the system. The design goals are often conflicting so that the improvement of one normally leads to a degradation of others. Compact microwave passives constitute a representative case: reduction of the circuit footprint area is detrimental to electrical figures of merit (e.g., the operating bandwidth). Identification of the best available trade-off designs requires multi-objective optimization (MO). This is a computationally expensive task, especially when executed at the level of full-wave electromagnetic (EM) simulation. The computational complexity issue can be mitigated through the employment of surrogate modeling methods, yet their application is limited by a typically high nonlinearity of system responses, and the curse of dimensionality. In this paper, a novel technique for fast MO of compact microwave components is proposed, which allows for sequential rendition of the trade-off designs using triangulation of the already available Pareto front as well as rapid refinement algorithms. Our methodology is purely deterministic; in particular, it does not rely on population-based nature-inspired procedures. The three major benefits are low computational cost, possibility of handling explicit design constraints, and a capability of producing a visually uniform representation of the Pareto front. The algorithm is demonstrated using a compact branch-line coupler and a three-section impedance matching transformer. In both cases, considerable savings are obtained over the benchmark, here, the state-of-the-art surrogate-assisted MO technique.

MMIG: Inversion optimization in majority inverter graph with minority operations

Majority inverter graph is a logic representation structure that along with its algebraic properties synthesizes circuits with improved area, delay, and speed metrics, as compared to conventional And-Invert graph (AIG) realization. In this paper, we propose mMIG synthesis approach, where we aim to minimize the number of inverters in such circuits by adopting minority logic in addition to majority and inversion operations in the logic representation. We propose a set of Boolean transformation methods and derived theorems for minority, majority, and inverter operations. We demonstrate that minority operation in addition to majority and inversion operations significantly optimizes the hardware footprint of combinational circuits and cryptographic primitives, such as linear operations and substitution boxes in several lightweight block ciphers. The area optimization is considered with reduction in count of complemented edges or inversion operations. As results demonstrate, the inversion operations have been reduced from 57 . 7% to 93 . 3% in mMIG synthesis approach as compared to MIG logic synthesis in EPFL combinational benchmark suite. In round function implementations of lightweight block ciphers such as SIMON, and ARX boxes such as MARX-2 and SPECKEY, the count of complemented edges in mMIG synthesis technique has been reduced by almost 50% as compared to that in MIG based implementations. • Inversion optimization is critical for reduced area in Majority Inverter Graph based logic synthesis. It reduces in net delay in the critical path and the total switching power of signals in the circuit. • Use of minority operations leads to additional set of transformation rules in Minority Majority Graph based logic synthesis. • Evaluation is performed on IWLS′05 benchmark circuits, arithmetic HDL benchmark circuits, EPFL combinational benchmark suites and lightweight cryptographic primitives.

(Invited) Simulation-Driven Optimization of Unconventional Digital Logic Devices

Organic thin-film transistor (OTFT) based electronics has been under extensive investigation over the last three decades. Dramatic improvements have been made during this time in terms of basic device performance and stability, yet a formidable challenge remains as to how to disentangle highly complex interplays between the materials properties, device layouts, and final circuit topologies, knowing that there are simply too may possible choices for synthetically diverse, solution-processable organic electronics. In this presentation, we highlight some of our latest researches on robust simulation-based design and realization of novel organic semiconductor logic systems. We first demonstrate the possibility of guided data-level matching at the organic lateral heterojunction ternary inverters that utilize a charge anti-ambipolarity. Here, it is found that controlling the energetic diffusion barrier and minority carrier mobility is the key to obtain the evenly distributed logic values. We then switch the topic to the recently reported 3-D complementary inverter circuits where the p-type and n-type transistors are vertically integrated with a reduced circuit footprint. We focus on the critical effects of the charge injection barriers into the unintentionally doped organic semiconductors, and reveal that the systematic contact efficiency variation leads to a largely improved signal amplification gain, as well as un unusual development of the multi-valued logic behaviors up to the quaternary level. Such results clearly demonstrate that physically-based device simulation has a strong capability of correlating various influential parameters at relevant focus levels, thus paving the way toward a totally predictive engineering paradigm of new materials-based electronics platforms.

Design and fabrication of a 6dB compact directional coupler

In this paper, we will present a planar geometry design for a 6dB compact microwave coupler, and will further explore and discuss the results of an electromagnetic simulation in Sonnet® Suites™ Electromagnetic simulation software. Being a compact coupler, the device features a minute circuit footprint size, while still observing the limitations of the production technologies involved in manufacturing it. The technology utilized in the paper is a 4 port microstrip copper trace on a production-friendly and extremely economical FR4 dielectric substrate. The circuit shows excellent performance in a 1.8GHz bandwidth (3.9GHz – 5.7GHz), with a loss of 6dB on the coupled port. A further advantage of this geometry is a very linear and predictable change in the S-parameter values as a result of small linear changes in the geometry

Erratum to: Ultrathin flexible InGaZnO transistor for implementing multiple functions with a very small circuit footprint

There is a continuous demand to reduce the size of the devices that form a unit circuit, such as logic gates and memory, to reduce their footprint and increase device integration. In order to achieve a highly efficient circuit architecture, optimizations need to be made in terms of device processing. However, the time involved in the current reduction of device sizes according to Moore’s Law has slowed down. Here, we propose a flexible transistor with ultra-thin IGZO (InGaZnO, indium-gallium-zinc-oxide) as the channel material, which not only scales down the footprints of multi-transistor logic gates but also combines the functions of the logic gates, memory, and sensors into a single cell. The transistor proposed here has an ultrathin semiconductor layer and can implement the typical functions of logic gates that conventionally have 2–6 transistors. Furthermore, it demonstrates the memory effect with a programming time as low as 5 ns. This design can also display various artificial synaptic behaviors. This new device design and structure can be adopted for the development of next-generation flexible electronics that require higher integration.

An Ultra-Low Cost Multilayer RAM in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is an alternative nanotechnology to traditional CMOS technology. In theory, circuits in QCA have the advantages of lower power consumption, higher integration density and switching frequency than circuits based on CMOS. Random access memory (RAM) circuits that are critical in designing large memory circuits have been explored. In this brief, a novel loop-based RAM cell with asynchronous set and reset, by using a new 2-1 multiplexer and D-latch, is proposed. Efficient 1 $\times $ 4 RAM and 4 $\times $ 4 RAM with three-layer structure are constructed. The proposed RAM cell has 35% improvement in both circuit footprint and cost, compared with an existing best scheme. The 1 $\times $ 4 RAM has less cells, delay and area than the previous designs with the same circuit scheme. The 4 $\times $ 4 RAM and ${m}\,\,\times \,\,{n}$ RAM show that the proposed RAM cell has excellent scalability for designing complex circuits. Functional correctness of the proposed designs has been proved by using QCADesigner 2.0.3.

Ultrathin flexible InGaZnO transistor for implementing multiple functions with a very small circuit footprint

There is a continuous demand to reduce the size of the devices that form a unit circuit, such as logic gates and memory, to reduce their footprint and increase device integration. In order to achieve a highly efficient circuit architecture, optimizations need to be made in terms of device processing. However, the time involved in the current reduction of device sizes according to Moore’s Law has slowed down. Here, we propose a flexible transistor with ultra-thin IGZO (InGaZnO, indium-gallium-zinc-oxide) as the channel material, which not only scales down the footprints of multi-transistor logic gates but also combines the functions of the logic gates, memory, and sensors into a single cell. The transistor proposed here has an ultrathin semiconductor layer and can implement the typical functions of logic gates that conventionally have 2–6 transistors. Furthermore, it demonstrates the memory effect with a programming time as low as 5 ns. This design can also display various artificial synaptic behaviors. This new device design and structure can be adopted for the development of next-generation flexible electronics that require higher integration.

Implementing an Insect Brain Computational Circuit Using III-V Nanowire Components in a Single Shared Waveguide Optical Network.

Recent developments in photonics include efficient nanoscale optoelectronic components and novel methods for subwavelength light manipulation. Here, we explore the potential offered by such devices as a substrate for neuromorphic computing. We propose an artificial neural network in which the weighted connectivity between nodes is achieved by emitting and receiving overlapping light signals inside a shared quasi 2D waveguide. This decreases the circuit footprint by at least an order of magnitude compared to existing optical solutions. The reception, evaluation, and emission of the optical signals are performed by neuron-like nodes constructed from known, highly efficient III–V nanowire optoelectronics. This minimizes power consumption of the network. To demonstrate the concept, we build a computational model based on an anatomically correct, functioning model of the central-complex navigation circuit of the insect brain. We simulate in detail the optical and electronic parts required to reproduce the connectivity of the central part of this network using previously experimentally derived parameters. The results are used as input in the full model, and we demonstrate that the functionality is preserved. Our approach points to a general method for drastically reducing the footprint and improving power efficiency of optoelectronic neural networks, leveraging the superior speed and energy efficiency of light as a carrier of information.

A Hybrid Low-Cost Bandpass Filter With SAW Resonators and External Lumped Inductors Using a Dual-Coupling Scheme

A class of hybrid low-cost bandpass filter (BPF) with only two kinds of circuit components, straightforward design procedure, and miniaturized circuit footprint is presented. The proposed BPF is based on a hybrid module composed of one type of surface-acoustic-wave (SAW) resonator and one external lumped inductor. Compared with traditional SAW-resonator-based BPF devices, the use of a single-SAW-resonator model for its design reduces the cost and complexity by avoiding the need for well-matched SAW-resonator pairs. The engineered filter topology consists of a dual-path coupling scheme, in which one coupling path is simply a series-type SAW resonator and another path is made up of two SAW resonators that are intercoupled by means of an external inductor in the middle. Such coupling architecture generates two additional transmission zeros (TZs) that allow to increase the out-of-band power-rejection levels and enlarge the stopband bandwidth. A circuit analysis based on the even-/odd-mode method is applied to derive its equivalent circuit that can be directly matched to a conventional transversal filter topology. The obtained equivalent circuit readily illustrates the operational mechanisms of the proposed filter principle in terms of reflection zeros and TZs. Subsequently, the quality factors of its even- and odd-mode-subnetwork resonators are analytically derived, and the obtained numerical results determine the tradeoff existing when choosing the external-inductor value among various performance metrics. For experimental validation purposes, two 418-MHz BPF prototypes formed by one and two in-series-cascade-connected second-order filtering units, respectively, are manufactured and tested. The circuit footprints of these filters are largely reduced by using a three-layer lamination technique for their physical implementations. The measured results show sharp-rejection filtering responses and are in close agreement with the theoretical predictions.

Ultra-thin silicon-on-insulator waveguide bend based on truncated Eaton lens implemented by varying the guiding layer thickness

Silicon-on-insulator (SOI) waveguides with different geometries have been employed to design various integrated optical components. Reducing the bending radius of the SOI waveguides with low bending loss is essential in minimizing the footprint of light-wave circuits. The propagating mode is less confined in the core of the ultra-thin SOI waveguide and penetrates to substrate and cladding, leading to higher bending loss compared with conventional SOI waveguide with the thicker guiding layer. While various bending mechanisms have been utilized to reduce the bending loss of conventional SOI waveguides, the ultra-thin SOI waveguide bends have not been studied in detail. In this paper, we present a 60 nm-thick SOI waveguide bend based on the truncated Eaton lens implemented by varying thickness of the guiding layer. The three-dimensional full-wave simulations reveal that the designed waveguide bend, with a radius of 3.9 $\mu m$, reduces the bending loss from 3.3 to 0.42 dB at the wavelength of 1550 nm. Moreover, the bending loss for the wavelength range of 1260-1675 nm is lower than 0.67 dB while the bending loss in the C-band is lower than 0.45 dB.

Broadband RF-to-DC Rectifier With Uncomplicated Matching Network

A novel broadband RF-to-DC rectifier using an uncomplicated matching approach is proposed and tested. The proposed rectifier is based on a voltage doubler-type configuration and broadband matching is achieved by simply adding two inductors in series with each of the diodes, canceling out the large capacitance inherent in the diodes as well as producing resonances over a wide bandwidth. This uncomplicated matching network allows for a smaller circuit footprint while providing a wide bandwidth. The proposed rectifier is validated via simulation and measurement. The results demonstrate that a rectification efficiency of more than 50% is maintained over a bandwidth of approximately 83% (0.54–1.3 GHz) at 5-dBm input power, with the maximum rectification efficiency of 80% at 10-dBm input power.