MMIG: Inversion optimization in majority inverter graph with minority operations

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Majority inverter graph is a logic representation structure that along with its algebraic properties synthesizes circuits with improved area, delay, and speed metrics, as compared to conventional And-Invert graph (AIG) realization. In this paper, we propose mMIG synthesis approach, where we aim to minimize the number of inverters in such circuits by adopting minority logic in addition to majority and inversion operations in the logic representation. We propose a set of Boolean transformation methods and derived theorems for minority, majority, and inverter operations. We demonstrate that minority operation in addition to majority and inversion operations significantly optimizes the hardware footprint of combinational circuits and cryptographic primitives, such as linear operations and substitution boxes in several lightweight block ciphers. The area optimization is considered with reduction in count of complemented edges or inversion operations. As results demonstrate, the inversion operations have been reduced from 57 . 7% to 93 . 3% in mMIG synthesis approach as compared to MIG logic synthesis in EPFL combinational benchmark suite. In round function implementations of lightweight block ciphers such as SIMON, and ARX boxes such as MARX-2 and SPECKEY, the count of complemented edges in mMIG synthesis technique has been reduced by almost 50% as compared to that in MIG based implementations. • Inversion optimization is critical for reduced area in Majority Inverter Graph based logic synthesis. It reduces in net delay in the critical path and the total switching power of signals in the circuit. • Use of minority operations leads to additional set of transformation rules in Minority Majority Graph based logic synthesis. • Evaluation is performed on IWLS′05 benchmark circuits, arithmetic HDL benchmark circuits, EPFL combinational benchmark suites and lightweight cryptographic primitives.