Threshold Voltage Fluctuations Research Articles

Nanogap resistive switch mechanism study and performance degradation analysis

The nanogap resistive switch holds potential as a candidate for nonvolatile memory, although its durability needs enhancement. This study delves into the operational mechanisms through detailed morphological examination during continuous operation of nanogap resistive switches. By developing a finite element model of nanogaps, we reveal the mechanisms behind the formation of electrode surface hillocks and filaments during continuous switching. Our findings suggest that “set” operations include processes such as field evaporation, electric field-induced diffusion, and field-assisted migration within the gap. Conversely, “reset” operations, driven by Joule heating and electromigration, lead to filament breakage and the creation of a fine gap. This research elucidates device degradation issues, such as periodic fluctuations in set threshold voltage (Vset) and the presence of non-steep set curves, providing both theoretical and experimental insights to improve future device performance.

On Reducing LDE Variations in Modern Analog Placement

Layout-dependent (LDEs) introduce an inevitable performance degradation in analog and mixed-signal circuit design with advanced process technologies below 90 nm. The main LDE sources, including the well proximity effect (WPE), length of diffusion (LOD), and the oxide-to-oxide spacing effect (OSE), cause substantial fluctuations in carrier mobility and threshold voltage of transistors. In traditional design flows, impact of these in post-layout simulation, leading to expensive re-design iterations by inspecting the physical locations of devices with respect to one another. In this article, we introduce the concept of an ideal mobility multiplier based on physics models, in order to minimize the LDE effects with a fast simulated annealing algorithm through various LDE alleviating operations. Based on the introduced mobility multiplier and the hierarchical B*-tree (HB*-tree) topological representation, our LDE-aware analog placement methodology can simultaneously optimize not only the area and wire length, but also the LDEs, while maintaining linear-packing time complexity of HB*-trees. Compared to the most recent works on 65 nm-based analog circuits, experimental results show that the proposed method can effectively and efficiently reduce LDE variations, while improving the circuit performance.

Design and fabrication results of Z-gate layout MOSFETs for radiation hardness integrated circuit

A Z-gate layout MOSFET (ZLT) is expected to reduce the total ionizing dose effects which occur in the shallow trench isolation layer made of oxide. To verify the ZLT’s merit, the ZLT was designed and fabricated with the 0.18 μm standard CMOS technology. The ZLT was irradiated with 60Co γ-rays up to 10 Mrad, and its I–V characteristic fluctuation was compared with that of a standard straight gate layout MOSFET (SLT). As a result, it was confirmed that the Z-gate can suppress off-current fluctuations by 1/5, on-current fluctuations by 1/2 and threshold voltage fluctuations by 1/6 compared with the SLT. Since the size penalty of the ZLT is small, it is possible to improve the radiation hardness of the CMOS LSI circuit by just replacing SLTs with ZLTs.

Multilayer doped-GeSe OTS selector for improved endurance and threshold voltage stability

Selector devices are indispensable components of large-scale memristor array systems. The thereinto, ovonic threshold switching (OTS) selector is one of the most suitable candidates for selector devices, owing to its high selectivity and scalability. However, OTS selectors suffer from poor endurance and stability which are persistent tricky problems for application. Here, we report on a multilayer OTS selector based on simple GeSe and doped-GeSe. The experimental results show improving selector performed extraordinary endurance up to 1010 and the fluctuation of threshold voltage is 2.5%. The reason for the improvement may lie in more interface states which strengthen the interaction among individual layers. These developments pave the way towards tuning a new class of OTS materials engineering, ensuring improvement of electrical performance.

Superiority of core–shell junctionless FETs

The core–shell structure brings fundamental advantages to junctionless (JL) MOSFETs. The addition of an undoped shell to a heavily doped core enables normally-off operation, high charge, excellent mobility, and very high current drive. The demerits of a classical JL transistor, such as poor mobility, negative threshold voltage and random dopant fluctuations (RDF), are eliminated while its attractive properties are maintained.

Compatible resistive switching mechanisms in Ni/SiOx/ITO and application to neuromorphic systems

In this work, we studied the switching mechanisms of Ni/SiOx/ITO devices before and after experiencing a reversible switching. And we also investigated its application for neuromorphic computing systems. First, we checked the composition of the device and progressed the electrical measurements. The device had two operating properties that are affected by an external applied voltage, and thus, we divided it into two distinct I-V curves to experimentally investigate the features. Even if they originated from the same RRAM devices, they exhibited different electrical measurements such as a retention, threshold voltages, and the conductance ratio. The I-V curve with an abrupt switching showed a good retention time of 7000 s and a wide conductance ratio of about ~41. On the other hand, the other I-V curve that shows progressive operation displayed a low retention time of 5000 s and a narrow conductance ratio of about ~3.43. We discussed the different results that were identified on the same device and concluded that it was caused by a change of switching mechanisms induced by a reversible switching in negative polarity. The overshoot current and large fluctuation in threshold voltage were used as evidence for our discussions. After identifying the electrical features, we progressed the biological processes such as potentiation/depression, paired-pulse facilitation (PPF) and spike-timing-dependent plasticity (STDP) to implement the neural networks.

Impact of stacking layers on RTN in 3D charge trapping NAND flash memory

The word-line (WL)-position dependence of memory cell's threshold-voltage fluctuation (ΔVth) in 3D charge trapping flash (CTF) caused by random telegraph noise (RTN) was studied. Contrary to planar NAND flash, test results show that WL0 has wider accumulative distributions of ΔVth than WL63 in 3D CTF NAND. Transmission electron microscopy (TEM) results show that grain size (GS) decreases by 14.6% from top WLs to bottom WLs. As a result, grain boundary density increases from top to bottom, which corresponds to a larger ΔVth. Moreover, despite the similar transconductance (Gm) trend in planar and 3D Flash memories, WL31's RTN hardly changed with altered RS and RD in CTF memory. These experimental results indicate that Gm is not the dominant factor of RTN in 3D CTF, but the physical properties of the polycrystalline silicon (poly-Si) channel.

A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-channel Eδ DC MOS Transistor

A drain current local variability compact model due to random fluctuation of channel length induced by line edge roughness/line width roughness (LER/LWR) is derived here. The random fluctuation of channel length leads to correlated fluctuations of threshold voltage and effective mobility of the current carriers. Therefore, an unified compact model is required to combine all the causes. Our model is based on the principle of propagation of variance. For the model verification purpose, calibrated technology computer aided design (TCAD) simulation platform is extensively used for all possible bias regions and several LER profile parameters. Channel profile optimization is critically studied with respect to different LER parameters, aiming reduction of ID variability. The model is further extended for SOI (Silicon-on-insulator) transistor and validated with literature data of threshold voltage and on-current variability.

TCAD-Based Investigation of Statistical Variability Immunity in U-Channel FDSOI n-MOSFET for Sub-7-nm Technology

In this article, the impact of random fluctuation sources, such as metal gate granularity (MGG), line edge roughness (LER), and random dopant fluctuations (RDFs), are numerically studied for U-shaped n-channel fully depleted silicon on insulator (FDSOI) MOSFET (U-SOIFET) over conventional n-channel FDSOI MOSFET (C-SOIFET) for 7-nm technology node. This article reports that improved short-channel effect immunity in U-SOIFET results in less $1\sigma $ threshold voltage ( ${V}_{T}$ ) and ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) fluctuations compared to C-SOIFET due to MGG and LER variability sources. U-SOIFET exhibits a low ${V}_{T}$ mismatch index ( ${A}_{\Delta VT}=1.78$ mV. $\mu \text{m}$ ) close to the literature reported. Due to combined variability sources, U-SOIFET shows less ${V}_{T}$ , ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , subthreshold swing (SS), and DIBL fluctuations compared to C-SOIFET. Immunity to statistical variability sources makes U-SOIFET a suitable silicon on insulator (SOI) device architecture for future CMOS logic device applications.

Investigation of process variation in vertically stacked gate-all-around nanowire transistor and SRAM circuit

An investigation into the intrinsic process variations including random dopant fluctuation (RDF), interface trap fluctuation, work-function variation (WFV) and oxide thickness variation was undertaken in a vertically stacked gate-all-around nanowire transistor. The fluctuation of the electrical characteristics induced by different sources of variation was discussed. The impact of process variations on static random access memory (SRAM) was also studied. On-state current could be affected by RDF in the source and drain region and the standard deviation can reach 17.2% of the median. WFV can cause obvious fluctuations in threshold voltage and consequently in the read static noise margin (RSNM) of SRAM. It has been discovered that the RSNM was deteriorated by 6.8% by WFV, which causes great uncertainty among all variation sources.

Vertically Stacked Gate-All-Around Structured Tunneling-Based Ternary-CMOS

This article proposes a novel structure for tunneling-based ternary-complementary metal-oxide-semi conductor (T-CMOS) to break through the power scaling constraints of conventional binary-CMOS. The previous T-CMOS uses off-leakage band-to-band tunneling (BTBT) currents generated at the deep drain-to-substrate junction for the third voltage state, which allows ternary inverter configuration with only two single transistors. However, the high-dose ion implantation for the BTBT layer must affect the channel doping concentration, leading to the threshold voltage fluctuation. To avoid the interference of the BTBT layer dopants to the channel as well as to maximize the electrostatic gate controllability, vertically stacked gate-all-around (GAA) field-effect transistor (GAAFET)-type T-CMOS device is proposed. By simply changing the ground plane (GP) doping concentration in existing GAAFET fabrication, the BTBT layer can be formed completely apart from the suspended channel layers. The changes of the transfer characteristics and the transient output voltage characteristics depending on the key parameters such as the GP doping concentration and the gate work function are thoroughly analyzed for the proposed GAA T-CMOS through mixed-mode TCAD device and circuit simulations. It is concluded that the two key parameters should be optimized, otherwise the margin for the third voltage state and the switching speed is seriously degraded.

Variability Effects in Nanowire and Macaroni MOSFETs—Part I: Random Dopant Fluctuations

In this article and the related Part II, we investigate variability effects on the threshold voltage of nanowire and Macaroni MOSFETs, focusing on random dopant fluctuations (RDFs) and random telegraph noise, to assess their dependences on device radius, channel length, and doping. In Part I, we address threshold voltage fluctuations induced by RDF and show that different trends emerge with respect to planar devices, being dependent on whether the conduction is bulk- or surface-dominated. Macaroni devices with thin silicon regions can improve RDF, while moving from inversion- to accumulation-mode devices results in a worsening of this parameter.

A physics-based model for LER-induced threshold voltage variations in double-gate MOSFET

The line-edge roughness (LER) has become one of the dominant sources of process variations in multi-gate transistors. The estimation of threshold voltage distribution due to LER through atomistic simulations is computationally intensive, even though these simulations provide accurate results. In this paper, a physics-based model for channel LER-induced threshold voltage fluctuations due to variations of the silicon-body thickness in a double-gate (DG) MOSFET is presented. The developed $$V_\mathrm{TH}$$ model gives more insights into the dependence of device and LER parameters on the $$V_\mathrm{TH}$$ variations with a reduced computational time. The computed $$V_\mathrm{TH}$$ variations due to different LER patterns are validated with TCAD simulations. The threshold voltage standard deviation due to LER in 500 device samples for different device dimensions, doping concentration and biases is studied. The developed model can be easily integrated in any circuit simulator to predict the threshold voltage variations of the devices due to LER.

Random telegraph noise in gate-all-around silicon nanowire MOSFETs induced by a single charge trap or random interface traps

The random telegraph noise (RTN) in gate-all-around (GAA) silicon (Si) nanowire (NW) metal–oxide–semiconductor field-effect transistors (MOSFETs) induced by a single charge trap (SCT) or random interface traps (RITs) is studied for the first time. An experimentally validated three-dimensional quantum-mechanically-corrected device simulation is advanced to investigate the explored devices. The magnitude of the RTN decreases with increasing gate voltage to different extents for the planar MOSFET, bulk FinFET, and GAA Si NW MOSFET devices, owing to the reduction in the conducting carriers along the channel. For the GAA Si NW MOSFET, the reduction of the fluctuation of threshold voltage in the presence of RITs is about 25 and 3 times when compared with the planar MOSFET and bulk FinFET device, respectively, whereas this reduction in the presence of an SCT is about 6 and 2.6 times, respectively. For the GAA Si NW MOSFET, the reduction of the RTN in the presence of RITs is about 7.5 and 4.7 times when compared with the planar MOSFET and bulk FinFET device, respectively, whereas this reduction in the presence of an SCT is about 22 and 6 times, respectively. At given threshold voltage, compared with the results for the planar MOSFETs and bulk FinFET, the GAA Si NW MOSFET exhibits minimal characteristic variability and RTN owing to the ultimate electrostatic control of the gate from the point of view of electrostatic integrity.

Investigation into trapping modes and threshold instabilities of state-of-art commercial GaN HEMTs

This work is aimed at investigating the performance and reliability limits of a commercially available state-of-the-art RF GaN HEMT technology. Measurement strategies to recognize and assess trap-induced degradations, prevalent in mature technologies, are discussed. Double pulsed measurements are used to capture and quantify threshold instabilities, and their evolution with temperature, for short quiescent near-threshold and off-state stress conditions. A versatile transient measurement technique evaluates threshold voltage fluctuations in the 10 μs–100 s temporal range, during stress or recovery phases, for different trap-filling configurations. Corresponding recovery transients between 27 °C to 130 °C are analysed to extract a trap activation energy of 0.53–0.56 eV for this technology. Finally, drain and gate step-stress tests are performed, providing an overview into the robustness of the gate contact under high electric fields.

Analytical modeling of random discrete traps induced threshold voltage fluctuations in double-gate MOSFET with HfO2/SiO2 gate dielectric stack

An analytical model of threshold voltage fluctuations due to random discrete traps at Si/SiO2 interface and in gate oxide regions for undoped double-gate (DG) MOSFET with high-k/SiO2 gate dielectric stack is presented in this paper. The model is derived based on the solution of 2-D Poisson's equation considering both position and number fluctuation of traps. The distribution of traps at the Si/SiO2 interfaces and in both gate oxide regions in double-gate structure are obtained using the bivariate Poisson distribution. The impact of interface and oxide traps over the threshold voltage are analyzed separately and together for the samples of 500 devices. The results from the model are verified using 2-D TCAD simulation results for different trap position, trap density, device dimension and drain bias. Even though the variability due to traps present in the gate oxide is comparatively lesser than the interface traps, the effect of oxide traps located in the interfacial layer (SiO2) cannot be neglected. The device variability increases with the consideration of both interface and oxide traps simultaneously and the threshold voltage fluctuations (ΔVTH) reach maximum of 90 mV. The proposed model takes less computational time for the calculation of threshold voltage fluctuations due to discrete traps compared to the atomistic simulations and thus it is suitable for circuit simulation.

Analytical Model for RDF-Induced Threshold Voltage Fluctuations in Double-Gate MOSFET

In this paper, a physics-based threshold voltage model of symmetrical double gate (DG) MOSFET, including the random dopants in the channel is presented. The model is derived from the solution of 2-D Poisson’s equation and is suitable for circuit simulation. The average potential considering random dopants in the channel is used to calculate the threshold voltage and provides accurate results. The developed threshold voltage model is validated with TCAD simulations for different device dimensions and doping concentrations. The standard deviation ( ${\sigma } {\text{V}}_{\text{TH}}$ ) is calculated from a threshold voltage distribution of 200 devices. The proposed model is useful to simulate variations in a large number of devices with randomly placed dopants, with less computational time. The model is integrated in the Cadence circuit simulator and analyzed the effect of random dopant fluctuation-induced ${\text{V}}_{\text{TH}}$ variations of n-channel DG MOSFET in the inverter circuit.

Three-dimensional exploration of the origin of threshold voltage fluctuation of silicon-on-insulator triple-gate fin-type field-effect transistors caused by ion implantation to source and drain extensions

The origin of the Vth fluctuation induced by ion implantation (I/I) into the source and drain extensions (SDEs) of triple-gate (tri-gate) fin-type field-effect transistors has been three-dimensionally explored by both three-dimensional (3D) process and device simulations. The 3D electrostatic potential distributions in the whole Si channel fin are analyzed, and it is confirmed that the 3D electrostatic potential distribution of the lowest Vth sample is more undulated than that of the highest Vth sample due to implanted arsenic (As+) ions to the SDEs irrespective of the drain bias condition. We found also that the minimum of bottleneck barrier heights (BBHs) in the Si whole channel fin, which is called BBH3D,min, is strongly correlated with the Vth, and therefore is a strong indicator to study the Vth of the device. It now became obvious that the origin of the SDE I/I-induced Vth fluctuation is a variation of BBH3D,min in the whole channel for the first time. The obtained results are beneficial for the research and development of such future devices.

Impact of WFV on electrical parameters due to high-k/metal gate in SiGe channel tunnel FET

This paper presented findings on statistical impact of mole fraction (x) on threshold voltage, on current, and off current in high-k/metal gate SiGe channel Tunnel FET (TFET) due to work function variability (WFV) of the metal gate. The analysis was carried out for varying mole fractions (x), average grain sizes, and device dimensions, using 3D TCAD device simulator. Our investigation showed that the fluctuation in threshold voltage (σVT) is noticeably affected by x, and grain sizes of metal gate. However, for large grain size, there is insignificant variation in σVT with an increase in x. Moreover, the distribution of threshold voltage is close to Gaussian for small grain size and bimodal for large grain size. The variation in on current (σIon) increases by negligible amount whereas off current fluctuation (σIoff) decreases significantly with increase in x. Further, the fluctuation in σVT with channel width is significant, but negligible with gate length.

A Thermal-Aware Physical Space Reallocation for Open-Channel SSD With 3-D Flash Memory

3-D flash memory faces a number of challenges, including thermal issues and process variation. The high temperature will cause charge loss and lead to the fluctuation of threshold voltage. To address the thermal issue of 3-D flash memory, this paper presents ThermAlloc , a novel thermal-aware physical space allocation strategy for open-channel solid-state drive with 3-D charge trapping flash memory. ThermAlloc permutes the allocation of physical blocks. Consecutively accessed logical blocks are distributed to different physical locations in order to prevent the accumulation of hotspots. The objective is to postpone garbage collection operations and keep the distribution of block temperature well under control. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that ThermAlloc can reduce the peak temperature by 26.94% with 3.15% extra worst-case response time in comparison with the baseline scheme.