Abstract
The line-edge roughness (LER) has become one of the dominant sources of process variations in multi-gate transistors. The estimation of threshold voltage distribution due to LER through atomistic simulations is computationally intensive, even though these simulations provide accurate results. In this paper, a physics-based model for channel LER-induced threshold voltage fluctuations due to variations of the silicon-body thickness in a double-gate (DG) MOSFET is presented. The developed $$V_\mathrm{TH}$$ model gives more insights into the dependence of device and LER parameters on the $$V_\mathrm{TH}$$ variations with a reduced computational time. The computed $$V_\mathrm{TH}$$ variations due to different LER patterns are validated with TCAD simulations. The threshold voltage standard deviation due to LER in 500 device samples for different device dimensions, doping concentration and biases is studied. The developed model can be easily integrated in any circuit simulator to predict the threshold voltage variations of the devices due to LER.
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