Analytical modeling of random discrete traps induced threshold voltage fluctuations in double-gate MOSFET with HfO2/SiO2 gate dielectric stack

Abstract

An analytical model of threshold voltage fluctuations due to random discrete traps at Si/SiO2 interface and in gate oxide regions for undoped double-gate (DG) MOSFET with high-k/SiO2 gate dielectric stack is presented in this paper. The model is derived based on the solution of 2-D Poisson's equation considering both position and number fluctuation of traps. The distribution of traps at the Si/SiO2 interfaces and in both gate oxide regions in double-gate structure are obtained using the bivariate Poisson distribution. The impact of interface and oxide traps over the threshold voltage are analyzed separately and together for the samples of 500 devices. The results from the model are verified using 2-D TCAD simulation results for different trap position, trap density, device dimension and drain bias. Even though the variability due to traps present in the gate oxide is comparatively lesser than the interface traps, the effect of oxide traps located in the interfacial layer (SiO2) cannot be neglected. The device variability increases with the consideration of both interface and oxide traps simultaneously and the threshold voltage fluctuations (ΔVTH) reach maximum of 90 mV. The proposed model takes less computational time for the calculation of threshold voltage fluctuations due to discrete traps compared to the atomistic simulations and thus it is suitable for circuit simulation.