Threshold Voltage Fluctuations Research Articles

Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs

Statistical variability and reliability due to random discrete dopants (RDD), gate line edge roughness (LER), metal gate granularity and N/PBIT associated random charge trapping has limited the progressive scaling of bulk planar MOSFETs beyond the 20-nm technology node. In this paper, their impacts on device figures of merit are studied through comprehensive 3-D simulation. It is found that raised drain-bias can exacerbate threshold-voltage fluctuations, mainly due to LER and RDD. Subthreshold slope (SS) variations resulting from each variation source is studied: RDD and LER generate most of the SS variation and are primarily responsible for its skew. Drain induced barrier lowering (DIBL) is examined against each intrinsic variation source, and RDD and LER are found to cause most of the DIBL variability. The correlation of DIBL with threshold-voltage is fully analysed with respect to each source of statistical variability and reliability. Except for LER, all major sources of variability exhibit de-correlation of DIBL against threshold-voltage.

Evaluation of Digital Circuit-Level Variability in Inversion-Mode and Junctionless FinFET Technologies

In this paper, we develop an evaluation framework to assess variability in nanoscale inversion-mode (IM) and junctionless (JL) fin field-effect transistors (FinFETs) due to line edge roughness (LER) and random dopant fluctuation (RDF) for both six transistor (6T) static random access memory (SRAM) design and large-scale digital circuits. From a device-level perspective, JL FinFETs are severely impacted by process variations: up to 40% and 60% fluctuation in threshold voltage is observed from LER RDF. Conversely, results show that variability-induced shifts and broadening of timing and power in large-scale digital circuits are not significant and can be accommodated in the design budget. However, we find that LER has a large impact on static noise margin analysis of 6T SRAMs. Required V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ccmin</sub> values for SRAMs using JL devices reach up to 2× those implemented in conventional IM technologies. The yield for JL SRAM is completely compromised in the presence of realistic levels of LER and RDF. Fortunately, the impact of variability is somewhat reduced with scaling for JL designs; both LER and RDF induce less variation for the 15-nm node compared with the 32-nm node. The observed reduction in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ccmin</sub> with technology scaling suggests that digital circuits implemented with JL FinFETs may eventually offer the same level of operability as those based on IM FinFETs, especially in the presence of circuit-level SRAM robustness optimizations.

Impact of Source/Drain Junction and Cell Shape on Random Telegraph Noise in NAND Flash Memory

A comprehensive numerical study of threshold voltage fluctuation (ΔVT) in scaled NAND flash memory caused by random telegraph noise (RTN) and discrete dopant fluctuation (RDF) in both the channel and the cell-to-cell space [source/drain (S/D)] region was carried out. Following a three-dimensional (3D) Monte Carlo (MC) procedure, the statistical distribution of ΔVT is estimated, considering the effects of both the random placement of discrete doping atoms and a discrete single trap at the tunnel oxide/substrate interface. The result demonstrates the significant influence of the doping in the S/D regions. For the cells with and without an S/D junction, the electron concentration in the S/D region is determined by the pass voltage of the unselected cell (Vpass) and the neighboring cell VT (VT(n)), owing to the fringing fields of neighboring floating gates (FGs). As a result, ΔVT increases in the S/D region as Vpass - VT(n) decreases. The fluctuation amplitude strongly depends on the [single-trap RTN] position along the cell length (L) and width (W) directions. For the cell shape with rounding of the active area (AA) at the shallow trench isolation (STI) edge, the results indicate that the high ΔVT area moves from the AA edge towards the center area along the W-direction.

Statistical Investigation of Anomalous Fast Erase Dynamics in Charge Trapping NAND Flash

In nand Flash nonvolatile memories, the erase operation drives the memory cells threshold voltage toward negative values, barely representing a concern for multilevel architectures. However, during the analysis of the erase dynamics in charge trapping (CT) memory arrays using an incremental step pulse erase algorithm, it is found that a small population of memory cells ( ≈ 2%) may randomly exhibit anomalous fast erase dynamics, which causes threshold voltage fluctuations during cycling operations. The purpose of this letter is to provide a statistical characterization of this phenomenon in CT-nand Flash arrays, thus helping the comprehension of its underlying physical mechanisms.

The intrinsic parameter fluctuation on high-κ/metal gate bulk FinFET devices

In this work, based on the experimentally calibrated 3D device simulation, we for the first time estimate the impact of intrinsic parameter fluctuation on the electrical characteristic of 16-nm-gate TiN/HfO2 bulk FinFETs. The sources of intrinsic parameter fluctuation include the random discrete dopants, interface traps and work function differences, simultaneously. The full 3D simulated threshold voltage fluctuation, induced by the aforementioned random sources simultaneously, is 26.2 mV for the N-type bulk FinFET (and is 55.5 mV for the planar N-MOSFET). For the N-type bulk FinFET, the statistical sum of these fluctuations is 9.5% (and is 12.3% for the planar device) overestimation, compared with the full 3D simulation. One of the main reasons is the independence assumption on these random variables is destroyed owing to interactions to different extents among RDs, ITs and WKs. The coupled surface potentials cannot be simply estimated by using their statistical sum of individual random source. Under the same threshold voltage, compared with the result of the planar MOSFETs, more than 50% reduction on the threshold voltage fluctuation of the explored bulk FinFETs is observed owing to the benefit of 3D structural nature.

Performance Fluctuations in 10-nm Trigate Metal–Oxide–Semiconductor Field-Effect Transistors: Impact of the Channel Geometry

Off-current and threshold voltage fluctuations in trigate (TG), and single-gate (SG) silicon-on-insulator (SOI) MOSFETs with a gate length of 10 nm are studied by means of three-dimensional (3D) device simulations. Special emphasis is paid to the role of the channel design. We demonstrate that both geometry fluctuations and the presence of single charged impurities in the active device regions can easily alter the off-currents of SG and TG MOSFET designs that nominally meet the Ion/Ioff requirements by more than one order of magnitude. It will be shown that regarding the robustness against geometry fluctuations, neither the SG MOSFET nor one of the possible TG MOSFET designs can be preferred in general. The SG concept, however, turns out to be exceptionally robust against threshold voltage fluctuations caused by single charged impurities.

(Invited) Negative-Bias Temperature Instability – Insight from Recent Dynamic Stress Experiments

The purpose of this paper is to summarize key experimental evidences on the important role of hole trapping on negative-bias temperature instability (NBTI). For a long time, the focus of this research topic had been on interface degradation driven by hydrogen transport and hole trapping was regarded as a side effect arising out of fast measurement techniques proposed to mitigate the effect of recovery on measurement data. In recent studies, we showed that the threshold voltage (V t) fluctuations one typically observed under dynamic NBTI were mainly the result of hole trapping and not hydrogen-transport driven interface-state generation/passivation proposed earlier. In particular, the cyclical V t shifts and constant V t recovery are inconsistent with the basic principle of the hydrogen transport model. Such behaviors are better described in terms of hole trapping/detrapping at pre-existing oxide defects. We have also shown that interface degradation during NBTI stressing has no apparent impact on bulk (oxide) trap generation, i.e. interface trap generation does not lead to bulk trap generation. This result raises further questions on the validity of the hydrogen transport mechanism and the long standing hypothesis on hydrogen-induced bulk trap generation and gate oxide breakdown. Finally, it is shown that the transient hole trapping responsible for the V t shift fluctuations could be transformed into more permanent trapped holes under NBTI stressing. The extent of transformation is accelerated by a high oxide field and temperature. An excellent correlation with stress induced leakage current indicates that such transformation underlie the generation of bulk traps reported by earlier studies.

A Simple Circuit to Investigate Threshold Voltage Variation and Its Application in Monitoring Negative Bias Temperature Instability Degradation

This paper presents a test circuit which can be used to analyze the p-MOSFET threshold voltage (VT) shift and fluctuation. The proposed circuit includes two p-MOSFETs, series connection. Using the circuit, we can directly measure threshold voltage shift on the output side and gather fluctuation statistics of p-MOSFET devices. The principle and the sensitivity of this method are demonstrated, followed by simulation and experimental results. A predictive model of negative bias temperature instability (NBTI) is introduced to analyze the PMOS degradation under constant stress. The NBTI stress experimental results have shown that this circuit can monitor NBTI degradation accurately, and offer a significant improvement in efficiency over existing Id–Vg methods.

The mechanisms of random trap fluctuation in metal oxide semiconductor field effect transistors

An effect, called random trap fluctuation (RTF), is proposed to study the threshold voltage (Vth) fluctuation of metal oxide semiconductor field effect transistors (MOSFETs) under Fowler-Nordeim (FN) or hot carrier (HC) stress condition. Experiments have been demonstrated on n-channel MOSFETs, and it was found that not only the random dopant fluctuation (RDF) but also the stress-induced traps vary the Vth fluctuation. More importantly, the stress-induced trap barrier determines the Vth fluctuation. For devices after FN stress, Vth fluctuation is enhanced since the trap barrier regulates the transporting carriers. For devices after HC stress, Vth fluctuation is supressed since the carriers are backscattered into the channel by the trap barrier and fewer carriers with higher energy pass through the barrier. These results provide us a clear understanding on another source of Vth fluctuations in addition to the RDF as devices are further scaled.

Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32-nm FinFET Technologies

The variability impact of line edge roughness (LER) on sub-32-nm fin-shaped FET (FinFET) technologies is investigated from both device- and circuit-level perspectives using computer-aided design simulations. Resist-defined FinFETs exhibit sizeable device performance variation (up to 10% fluctuation in threshold voltage and 200% in leakage current) when subjected to fin roughness up to 1 nm root-mean-square amplitude. Spacer-defined FinFETs show negligible device performance variation and exhibit quadratic dependence with LER amplitude. For both patterning technologies, the resulting impact on large-scale digital-circuit performance variation is found to be minimal in terms of the overall delay mean and variation. This is attributed to self-averaging of uncorrelated LER effects between individual devices within the circuits, resulting in minimal delay impact for digital-circuit design. The impact of LER on leakage power variation is also found to be minimal for all technologies; however, the mean value increases by up to 40% for 15-nm resist FinFETs. On this basis, the impact of LER on sub-32-nm FinFET device-level variability is only significant for resist devices, whereas the resulting digital-circuit impact is important only in terms of mean leakage power increase.

Reduction of threshold voltage fluctuation in field-effect transistors by controlling individual dopant position

To investigate the impact of only the dopant position on threshold voltage (Vth) in nanoscale field-effect transistors, we fabricated transistors with ordered dopant arrays and conventional random channel doping. Electrical measurements revealed that device performance could be enhanced by controlling the dopant position alone, despite varying dopant number according to a Poisson distribution. Furthermore, device-to-device fluctuations in Vth could be suppressed by implanting a heavier ion such as arsenic owing to the reduction of the projected ion struggling. The results of our study highlight potential improvements in device performance by controlling individual dopant positions.

Statistical device simulation of physical and electrical characteristic fluctuations in 16-nm-gate high-κ/metal gate MOSFETs in the presence of random discrete dopants and random interface traps

We estimate the effects of random discrete dopants (RDs) and random interface traps (ITs) on physical and electrical characteristic fluctuations of 16-nm-gate high-κ/metal gate (HKMG) metal–oxide-semiconductor field effect transistors (MOSFETs). Two-dimensional (2D) random ITs at the hafnium oxide (HfO2)/silicon interface and 3D RDs inside the silicon channel of the 16-nm-gate HKMG MOSFETs are simultaneously incorporated into an experimentally validated 3D device simulation to quantify the RDs-and-ITs-fluctuated characteristics. The random effect of the combined RDs and ITs induces rather different fluctuation in the threshold voltage, the on-/off-state current, and the gate capacitance in the 16-nm-gate HKMG MOSFETs. The surface potential, DC and AC characteristic fluctuations are affected to different extents by the random combinatorial RDs and ITs. Nonlinearly correlated RDs and ITs violate the statistical assumption of independent identical distributions between the RDs- and ITs-induced random variables. Consequently, for the studied 16-nm-gate HKMG N-MOSFETs, the threshold voltage fluctuation induced by the combined RDs and ITs is 11% less than their statistical sum due to local interaction of surface potentials resulting from the RDs and ITs simultaneously. Similarly, it is about 8.9% for the P-MOSFET devices. Depending upon random position and number of the combined RDs and ITs, overestimation or underestimation between the statistical sum of variances and the 3D device simulation is also observed for the drain current and the gate capacitance.

Carbon nanotube based ultra-low voltage integrated circuits: Scaling down to 0.4 V

Carbon nanotube (CNT) based integrated circuits (ICs) including basic logic and arithmetic circuits were demonstrated working under a supply voltage low as 0.4 V, which is much lower than that used in conventional silicon ICs. The low limit of supply voltage of the CNT circuits is determined by the degraded noise margin originated from the process inducing threshold voltage fluctuation. The power dissipation of CNT ICs can be remarkably reduced by scaling down the supply voltage, and it is of crucial importance for the further developments of nanoelectronics ICs with higher integration density.

Threshold Voltage Fluctuation in 16-nm-Gate FinFETs Induced by Random Work Function of Nanosized Metal Grain

The random work-function (WK) induced threshold voltage fluctuation (sigmaVth) in 16 nm Titanium Nitride (TiN) metal-gate fin-type field effect transistors (FinFETs) is explored and modeled by using an experimentally validated Monte Carlo simulation approach. The influences of metal-grain size and device geometry aspect ratio on the random WK-induced sigmaVth are considered in the proposed equation analytically. The formula accounts for the inside of fluctuation and could be used for the assessment of effectiveness of suppression techniques.

Random Work-Function-Induced Threshold Voltage Fluctuation in Metal-Gate MOS Devices by Monte Carlo Simulation

In this paper, we estimate the effect of random work function (WK) on the threshold voltage fluctuation (σVth) of 16-nm-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with metal-gate materials. To examine the random WK induced σVth, nanosized metal grains with different gate materials are considered in a large-scale statistical simulation. An analytical expression of the WK induced σVth is proposed based on the Monte Carlo simulation results which can outlook different extents of fluctuation resulting from various metal gates and benefit the device fabrication. Devices with a two-layer metal-gate are further studied for fluctuation suppression; the finding of this paper indicates the first layer of the gate structure plays the most significant role in the suppression of the WK induced σVth, compared with the second layer. This paper provides an insight into random work-function-induced threshold voltage fluctuation, which can, in turn, be used to assess metal gate characteristics of MOSFETs.

40nm Low Power MOSFET Transistor VT Fluctuation Control

This paper presents an approach to reduce threshold voltage (VT) fluctuation in 40nm low power MOSFET transistor. Introducing nitrogen (N) co-implantation in pocket architecture and reducing pocket implant tilt angle are two factors known for decreasing the VT fluctuation (σVt). In this paper, we combined these two VT fluctuation reduction approaches in source and drain extension (SDE) process and demonstrated that it could not only improve VT mismatch (σVt) ~30%, but also reduce MOSFET overlay capacitance ~ 8%

Effect of Flash Lamp Annealing and Laser Spike Annealing on Random Dopant Fluctuation of 15-nm Metal-Oxide-Semiconductor Devices

Comparison of two different implantation processing techniques for random dopant (RD)-induced threshold voltage fluctuation (sigmaV(th)) in 15-nm metal-oxide-semiconductor (MOS) devices is reported. Implantations of flash lamp annealing and laser spike annealing are simulated using a kinetic Monte Carlo (KMC) technique. The KMC generated distributions are mapped into device channel for three-dimensional quantum mechanical transport simulation to estimate threshold voltage fluctuation. The main results of this study show that the laser spike annealing could achieve 30% reduction of RDF-induced sigmaV(th) for low-power application of 15-nm MOS devices, compared with flash lamp annealing.

Analysis of Threshold Voltage Variability Due to Random Dopant Fluctuations in Junctionless FETs

An analytical formulation of the threshold voltage variance induced by random dopant fluctuations in junctionless transistors is derived for both cylindrical nanowire and planar double-gate structures under uniform channel and constant mobility approximation. Results from drift-diffusion-based numerical methods are in reasonable agreement also for large , including mobility variations, and for short gate lengths. The results clearly indicate that the threshold voltage fluctuations can become a concern with the reduction of the critical dimensions.

Threshold Voltage Fluctuations in Localized Charge-Trapping Nonvolatile Memory Devices

Threshold voltage fluctuations are studied in localized charge-trapping nonvolatile memory devices. Intensive program/erase cycling followed by high-temperature bake shifts the mean Vt of programmed bits and increases the variance of the Vt distribution. After long enough bake, the Vt decay saturates, and the mean Vt and the variance stabilize. Upon continuing bakes, Vt's of individual bits are found to fluctuate up and down while the envelope remains fixed. The formation of a stable envelope of randomly fluctuating bits is modeled in terms of charge displacements of trapped electrons confined to the cells' nitride storage layer. Implications to product reliability under high-temperature stress are discussed.

A Comparative Study of NBTI and RTN Amplitude Distributions in High- $\kappa$ Gate Dielectric pMOSFETs

Random telegraph noise (RTN) and negative bias temperature (NBT) stress-induced threshold voltage (Vt) fluctuations in high-κ gate dielectric and metal-gate pMOSFETs are investigated. We measured RTN amplitude distributions before and after NBT stress. RTN in poststressed devices exhibits a broader amplitude distribution than the prestress one. In addition, we trace a single trapped charge-induced ΔVt in NBT stress and find that the average ΔVt is significantly larger than a ΔVt caused by RTN. A 3-D atomistic simulation is performed to compare a single-charge-induced ΔVt by RTN and NBTI. In our simulation, the probability distribution of a NBT trapped charge in the channel is calculated from the reaction-diffusion model. Our simulation confirms that the NBT-induced ΔVt indeed has a larger distribution tail than RTN due to a current-path percolation effect.