Threshold Voltage Fluctuations in Localized Charge-Trapping Nonvolatile Memory Devices

Abstract

Threshold voltage fluctuations are studied in localized charge-trapping nonvolatile memory devices. Intensive program/erase cycling followed by high-temperature bake shifts the mean Vt of programmed bits and increases the variance of the Vt distribution. After long enough bake, the Vt decay saturates, and the mean Vt and the variance stabilize. Upon continuing bakes, Vt's of individual bits are found to fluctuate up and down while the envelope remains fixed. The formation of a stable envelope of randomly fluctuating bits is modeled in terms of charge displacements of trapped electrons confined to the cells' nitride storage layer. Implications to product reliability under high-temperature stress are discussed.