Anomalous Threshold Voltage Variability of Nitride Based Charge Storage Nonvolatile Memory Devices

Meng Chuan Lee,Hin Yong Wong

doi:10.1155/2013/650457

Abstract

Conventional technology scaling is implemented to meet the insatiable demand of high memory density and low cost per bit of charge storage nonvolatile memory (NVM) devices. In this study, effect of technology scaling to anomalous threshold voltage (<svg style="vertical-align:-3.21404pt;width:17.4125px;" id="M1" height="15.4" version="1.1" viewBox="0 0 17.4125 15.4" width="17.4125" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,11.112)"><path id="x1D449" d="M730 650l-8 -28q-52 -4 -72 -18t-64 -77q-79 -113 -321 -539h-33l-119 541q-13 59 -29.5 73t-66.5 20l7 28h245l-8 -28l-28 -5q-33 -6 -40.5 -15.5t-0.5 -38.5l102 -450h2q191 320 246 430q21 42 15.5 56t-43.5 19l-31 4l7 28h240z" /></g> <g transform="matrix(.012,-0,0,-.012,12.675,15.187)"><path id="x1D461" d="M324 430l-26 -36l-112 -4l-55 -265q-13 -66 7 -66q13 0 44.5 20t50.5 40l17 -24q-38 -40 -85.5 -73.5t-87.5 -33.5q-50 0 -21 138l55 262h-80l-2 8l25 34h66l25 99l78 63l10 -9l-37 -153h128z" /></g> </svg>) variability is investigated thoroughly on postcycled and baked nitride based charge storage NVM devices. After long annealing bake of high temperature, cell’s <svg style="vertical-align:-3.21404pt;width:17.4125px;" id="M2" height="15.4" version="1.1" viewBox="0 0 17.4125 15.4" width="17.4125" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,11.112)"><use xlink:href="#x1D449"/></g> <g transform="matrix(.012,-0,0,-.012,12.675,15.187)"><use xlink:href="#x1D461"/></g> </svg> variability of each subsequent bake increases within stable <svg style="vertical-align:-3.21404pt;width:17.4125px;" id="M3" height="15.4" version="1.1" viewBox="0 0 17.4125 15.4" width="17.4125" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,11.112)"><use xlink:href="#x1D449"/></g> <g transform="matrix(.012,-0,0,-.012,12.675,15.187)"><use xlink:href="#x1D461"/></g> </svg> distribution and found exacerbate by technology scaling. Apparent activation energy of this anomalous <svg style="vertical-align:-3.21404pt;width:17.4125px;" id="M4" height="15.4" version="1.1" viewBox="0 0 17.4125 15.4" width="17.4125" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,11.112)"><use xlink:href="#x1D449"/></g> <g transform="matrix(.012,-0,0,-.012,12.675,15.187)"><use xlink:href="#x1D461"/></g> </svg> variability was derived through Arrhenius plots. Apparent activation energy (Eaa) of this anomalous <svg style="vertical-align:-3.21404pt;width:17.4125px;" id="M5" height="15.4" version="1.1" viewBox="0 0 17.4125 15.4" width="17.4125" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,11.112)"><use xlink:href="#x1D449"/></g> <g transform="matrix(.012,-0,0,-.012,12.675,15.187)"><use xlink:href="#x1D461"/></g> </svg> variability is 0.67 eV at sub-40 nm devices which is a reduction of approximately 2 times from 110 nm devices. Technology scaling clearly aggravates this anomalous <svg style="vertical-align:-3.21404pt;width:17.4125px;" id="M6" height="15.4" version="1.1" viewBox="0 0 17.4125 15.4" width="17.4125" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,11.112)"><use xlink:href="#x1D449"/></g> <g transform="matrix(.012,-0,0,-.012,12.675,15.187)"><use xlink:href="#x1D461"/></g> </svg> variability, and this poses reliability challenges to applications that demand strict <svg style="vertical-align:-3.21404pt;width:17.4125px;" id="M7" height="15.4" version="1.1" viewBox="0 0 17.4125 15.4" width="17.4125" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,11.112)"><use xlink:href="#x1D449"/></g> <g transform="matrix(.012,-0,0,-.012,12.675,15.187)"><use xlink:href="#x1D461"/></g> </svg> control, for example, reference cells that govern fundamental program, erase, and verify operations of NVM devices. Based on critical evidence, this anomalous <svg style="vertical-align:-3.21404pt;width:17.4125px;" id="M8" height="15.4" version="1.1" viewBox="0 0 17.4125 15.4" width="17.4125" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,11.112)"><use xlink:href="#x1D449"/></g> <g transform="matrix(.012,-0,0,-.012,12.675,15.187)"><use xlink:href="#x1D461"/></g> </svg> variability is attributed to lateral displacement of trapped charges in nitride storage layer. Reliability implications of this study are elucidated. Moreover, potential mitigation methods are proposed to complement technology scaling to prolong the front-runner role of nitride based charge storage NVM in semiconductor flash memory market.

Highlights

With the advancement of lithography techniques, conventional technology scaling that aggressively scaled down physical dimension of nonvolatile memory (NVM) devices has always been the key strategy to meet the demand for high memory density, low cost per bit, and excellent reliability charge storage NVM devices
As reported by Honda and Cho, electrons were observed in nitride layer of ONO film, while holes were found in nitride layer and tunnel oxide layer by using scanning nonlinear dielectric microscopy (SNDM) [2]
This instead indicates that vertical charge leakage through Frenkel-Poole (FP) emission followed by trap assisted tunneling (TAT) is ruled out as contributor to anomalous Vt variability at SE steady phase [8,9,10,11]

Summary

Introduction

With the advancement of lithography techniques, conventional technology scaling that aggressively scaled down physical dimension of nonvolatile memory (NVM) devices has always been the key strategy to meet the demand for high memory density, low cost per bit, and excellent reliability charge storage NVM devices. Floating gate (FG) and nitride based charge storage NVM devices are among the front runners of NVM devices in the rapid evolution of smart consumer electronics. The storage media of FG device is conductive polysilicon, and the storage media for nitride based charge storage NVM device is the low conductivity nitride layer sandwiched between oxide layers. As reported in [1], the Achilles’ heel for FG devices is susceptible to point defects that may drain out all charges from conductive polysilicon layer through percolation paths formed by these point defects in tunnel oxide. The trapped charges do not migrate much laterally due to the low conductivity behavior of silicon nitride that causes nitride based charge storage NVM immune to point defects that plagues FG devices [3]. During P/E cycling, both injected electrons and holes coexisted within nitride storage layer while only holes exist in tunnel oxide layer [2]

Methods

Results

Conclusion