Floating-gate Research Articles

A comparative analysis and an optimized structure of vertical GaN floating gate trench MOSFET for high-frequency FOM

A vertical GaN floating gate trench MOSFET (FG-MOSFET) device structure has been optimized to obtain an enhanced high-frequency figure of merit (HF-FOM) than the conventional SGT- and TG-MOSFET. The floating gate (FG) electrode helps to reduce the surface electric field and binges in the middle of the drift layer. Using TCAD simulation, we demonstrate that with proper design of trench depth, drift doping, and field plate oxide thickness, the corresponding electric-field distribution for FG-MOSFET can be reduced to 2.3 MV cm−1. The proposed device has been designed for 600 V blocking voltage capability and with a specific on-resistance () as low as 0.73 mΩ cm2 due to the higher drift doping concentration. The HF-FOM () of FG-MOSFET shows a lower by two times and four times compared to SGT- and TG-MOSFET, due to FP oxide. Our results show that the FG-MOSFET device produces 15% and 47% reductions in the switching energy losses when compared with the similar current rated SGT- and TG-MOSFET devices, respectively.

The DIME-1 Experiment Flown as Part of NASA’s SET-1 Project on the DSX Satellite

Dosimetry Intercomparison and Miniaturization Experiment (DIME-1) is an experiment flying as part of NASA’s Space Experimental Testbed (SET-1) satellite project on the Air Force’s Demonstration and Science Experiments (DSX) satellite to compare novel dosimeters with the standard radiation field-effect transistor (RadFET) dosimeters. It consists of five operational RadFETs under different thicknesses of hemispherical Al and Ta shields and three commercial-off-the-shelf (COTS) floating-gate MOS transistor (FGMOS) UV Proms programmed as dosimeters. The flight path crosses the entire slot region and cuts the Van Allen belts on each 5.25-h orbit of the Earth. The dosimeters on DIME-1 and its sister board DIME-2, consisting of two linear energy transfer (LET) spectrometers, are capable of measuring total ionizing dose (TID) and single-event effects (SEEs) which are responsible for degrading or causing catastrophic failure of electronic circuits in space. Results comparing the different dosimeters with the standard RadFET devices are shown to be in quite good agreement in terms of the shape of the total dose versus time plots over the 1.75 year life of the DSX mission but not in agreement over the TID measured presumably due to short-range protons reaching the sensitive volume of FGMOS devices but not reaching that of RadFETs. DIME-1 traveled into a radiation environment that well-designed circuits, flown during solar minimum, will survive.

Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors

Multi-valued logic (MVL) circuits based on heterojunction transistor (HTR) have emerged as an effective strategy for high-density information processing without increasing the circuit complexity. Herein, an organic ternary logic inverter (T-inverter) is demonstrated, where a nonvolatile floating-gate flash memory is employed to control the channel conductance systematically, thus realizing the stabilized T-inverter operation. The 3-dimensional (3D) T-inverter is fabricated in a vertically stacked form based on all-dry processes, which enables the high-density integration with high device uniformity. In the flash memory, ultrathin polymer dielectrics are utilized to reduce the programming/erasing voltage as well as operating voltage. With the optimum programming state, the 3D T-inverter fulfills all the important requirements such as full-swing operation, optimum intermediate logic value (~VDD/2), high DC gain exceeding 20 V/V as well as low-voltage operation (< 5 V). The organic flash memory exhibits long retention characteristics (current change less than 10% after 104 s), leading to the long-term stability of the 3D T-inverter. We believe the 3D T-inverter employing flash memory developed in this study can provide a useful insight to achieve high-performance MVL circuits.

Fabrication and optimization of aggressively scaled Dual-Bit/Cell Split-Gate Floating-Gate flash memory cell in 55-nm node technology

An aggressively scaled triple self-aligned split-gate floating-gate (FG) NOR-type Dual-bit/cell (NORD) flash cell was studied and fabricated at 55-nm node technology. Both FG- and selected-gate (SG-) length, for the first time, were scaled down to sub-80 nm and sub-60 nm in NORD flash, respectively. In this paper, performance of aggressively scaled cells were demonstrated by measurements. Firstly, the cell’s characteristics were presented by discussing FG- and SG-transistor’s drain-induced barrier lowering (DIBL) effects and SG-FG coupling effect. It was experimentally revealed that excellent immunity of DIBL effect was still obtained in this highly scaled SG-transistor due to the fully isolated SG-channel. Then, optimization from process for FG-transistor had been discussed. It was shown that the properties of subthreshold region of FG-transistor has been improved by introducing dual pocket implants for the half-isolated FG-channel. Thirdly, reading biases were also studied to expand the window of read currents. A novel cell structure was also proposed to further improve the aggressively length-scaled NORD flash cell without sacrificing bit-area. Finally, the reliability characteristics were also presented.

A New Design for Compact Floating-Gate Transistor Based Low-Voltage Four-Quadrant Analog Current Multiplier

A New Design for Compact Floating-Gate Transistor Based Low-Voltage Four-Quadrant Analog Current Multiplier

Low Voltage High Performance Floating Gate and Quasi Floating Gate CDTA

A low voltage and low power current differencing transconductance amplifier (CDTA) based on Floating gate MOSFET (FGMOS) and Quasi-floating gate MOSFET (QFGMOS) is presented. The use of QFGMOS eliminates confined in the floating gate, degraded gain-bandwidth product, silicon area etc. The proposed circuits have been simulated using spice simulation software 180nm technology of analog devices LtSpice XVII and supply voltage used for this is ±1V.

Multifunctional Half-Floating-Gate Field-Effect Transistor Based on MoS2-BN-Graphene van der Waals Heterostructures.

Multifunctional electronic devices that combine logic operation and data storage functions are of great importance in developing next-generation computation. The recent development of van der Waals (vdW) heterostructures based on various two-dimensional (2D) materials have brought exceptional opportunities in designing novel electronic devices. Although various 2D-heterostructure-based electronic devices have been reported, multifunctional devices that can combine logic operations and data storage functions are still quite rare. In this work, we design and fabricate a half-floating-gate field-effect transistor based on MoS2-BN-graphene vdW heterostuctures, which can be used for logic operations as a MOSFET, nonvolatile memory as a floating-gate MOSFET (FG-MOSFET), and rectification as a diode. These results could lay the foundation for various applications based on 2D vdW heterostuctures and inspire the design of next-generation computation beyond the von Neumann architecture.

Bionic artificial synaptic floating gate transistor based on MXene

The ability to simulate biological neurobehavior with electronic devices has now attracted widespread attention. In the past few decades, people have tried a variety of device structures to simulate biological synaptic functions. Due to floating gate thin-film transistors' robust charge blocking and the existence of the tunneling layer, the trapped charge can be stored in a non-volatile manner, which has been considered one of the most suitable device structures for manufacturing artificial synapses. In this work, a photoelectric-stimulated artificial synaptic thin-film transistor was proposed. The MXene and self-assembled titanium dioxide on the surface serves as the floating gate layer and the tunneling layer, respectively. Moreover, the typical synaptic behaviors of synaptic transistors, such as excitatory postsynaptic current and paired-pulse facilitation, have been proven through electrical and optical pulse tests. Finally, through the simulation based on Butterworth's high-pass filter, the input images could be successfully sharpened. The characteristics of these photoelectric synapses reveal the huge potential of this device in neuromorphic vision applications. This work provides a very feasible solution for the application of artificial synaptic devices to image processing and recognition.

Flexible organic field-effect transistor nonvolatile memory enabling bipolar charge storage by small-molecule floating gate

A nonvolatile memory based on the floating-gate organic field-effect transistor was prepared by using the vacuum thermal evaporation taking small-molecule fullerenes (C60) as the floating-gate layer and long-chain alkane molecule tetratetracontane as the tunneling layer. Intrinsic correlations between microstructures of the floating gate and the memory performance, the physical mechanisms of the carrier injection, transfer, and storage, and the relationships between the charge-trapping capability of the floating-gate layers of different thicknesses made of small-molecule C60 and key parameters of the memory were investigated. The results show that the memory covers the charges stored in the manner of the opposite polarity during operation under the programming and erasing voltages. The bipolar charges (electrons and holes) are injected and captured in the floating gate. After optimization, the high-performance memory has an average memory window of 6.5 V, remains stable for more than one year, and is reliable for more than 220 programming/erasing cycles. Moreover, the memory also has excellent endurance to mechanical bending and retains favorable storage stability after being compressed or tensed 500 times to a bend-radius of 5 mm.

Photoelectric Logic and In Situ Memory Transistors with Stepped Floating Gates of Perovskite Quantum Dots.

Electronic-Photonic integrated systems have attracted intensive attention in addressing the explosively increasing data-processing issue in the post-Moore era. However, the tremendous size difference between basic electronic and photonic units poses challenges for the further deep convergence of optoelectronic microprocessors. Here, we report a floating-gate transistor fabricated with complementary metal-oxide-semiconductor compatible technologies, which can realize multilevel photoelectric logic computing and in situ memory simultaneously. The transistor presents stepped floating gates of perovskite quantum dots with different bandgaps and exhibits nonvolatile multilevel memory states written/erased by electrical and high-bandwidth optical signals. Meanwhile, the device can also realize logic functions such as an optoelectronic AND gate by separably programming the states of the stepped floating gates with bias and optical wavelength. A convergence of multilevel logic computing and storage is further achieved on the transistor. By demonstrating such multifunctionality in a single device, the photoelectric transistors, even with a rather large size to match photonic cells, can provide the optoelectronic microprocessors with substantially improved performances.

Triboelectric Nanogenerators as Active Tactile Stimulators for Multifunctional Sensing and Artificial Synapses.

The wearable tactile sensors have attracted great attention in the fields of intelligent robots, healthcare monitors and human-machine interactions. To create active tactile sensors that can directly generate electrical signals in response to stimuli from the surrounding environment is of great significance. Triboelectric nanogenerators (TENGs) have the advantages of high sensitivity, fast response speed and low cost that can convert any type of mechanical motion in the surrounding environment into electrical signals, which provides an effective strategy to design the self-powered active tactile sensors. Here, an overview of the development in TENGs as tactile stimulators for multifunctional sensing and artificial synapses is systematically introduced. Firstly, the applications of TENGs as tactile stimulators in pressure, temperature, proximity sensing, and object recognition are introduced in detail. Then, the research progress of TENGs as tactile stimulators for artificial synapses is emphatically introduced, which is mainly reflected in the electrolyte-gate synaptic transistors, optoelectronic synaptic transistors, floating-gate synaptic transistors, reduced graphene oxides-based artificial synapse, and integrated circuit-based artificial synapse and nervous systems. Finally, the challenges of TENGs as tactile stimulators for multifunctional sensing and artificial synapses in practical applications are summarized, and the future development prospects are expected.

A Stochastic Leaky-Integrate-and-Fire Neuron Model With Floating Gate-Based Technology for Fast and Accurate Population Coding

An analytical model has been developed for stochastic leaky-integrate-and-fire (LIF) neurons with floating gate (FG) technology. The stochastic behaviors have been modeled extensively for both individual neurons and populations of neurons. In the FG LIF neurons, the electron injection is governed by the tunneling process through the gate oxide, leading to the exponential distributions of the injection time and inter spike interval (ISI) stochasticity. The concept of the population coding is demonstrated by simulating the stochastic behaviors of the populations of the FG LIF neurons. The ISI stochasticity enables encoding of the input signals to the population outputs. Spike-to-spike stochasticity improves the signal-to-noise ratio of the population outputs. Moreover, the shape of the ISI distribution can be controlled by adjusting the number of electrons to spike (NES). Exponential-like ISI distributions are realized by reducing the NES. With the exponential-like ISI distributions, the population of fast spiking neurons increases significantly (more than 10% of neurons spiking twice faster than the mean ISI), potentially contributing to the fast computation. Finally, step-by-step procedures have been proposed to design the FG LIF neurons exhibiting the desired neuron characteristics including operation voltage (0.5 V to 3 V), leaky time constant <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$( { &lt; } 1~ {\mathrm {\mu }}\text{s}$ </tex-math></inline-formula> to >10 ms), ISI mean (in the range of 6 orders of magnitude) and stochasticity ~0 % to ~60 %) as well as the type of the distribution (exponential-like to Gaussian-like).

Programmable linear random-access memory and its in-memory computing circuits and systems based on flash memory

The neural network inference chips based on novel non-volatile memories and compute-in-memory architectures have exhibited significant advantages in terms of power consumption, computation speed and storage density, making them a widely-attractive candidate for IoT and edge computing applications. In this paper, we introduced the design and implementation of an in-memory computing SoC chip based on modified floating-gate transistor devices named PLRAM. In order to achieve highly-efficient inference computation under constrained resources, this system combines a series of techniques from the device, circuit and system perspectives, including: new devices with 7 bit/cell storage capability, self-adaptive write of data, compensation of circuits mismatch and model deployment techniques based on training residual models. These new techniques helped the system to achieve superb overall performance, including compact form factor, energy efficiency above 10 TOPS/W and computation accuracy of roughly 95%. It has been successfully used in low-power, low-cost products for keyword-spotting applications.

Transparent Floating Gate Memory Based on ZnO Thin Film Transistor With Controllable Memory Window

The transparent floating gate memory based on zinc oxide (ZnO) thin film transistors (TFTs) was fabricated by using one-step atom layer deposition of aluminia tunneling and ZnO charge-trap layers. Free electrons trapping mechanism of this memory device is proposed after systematical investigation of gate voltage scanning and thickness of the trapping layer. Furthermore, the relationship between the geometrical size of the charge-trapping layer and the memory window is explored. The devices with different memory windows can be controlled simply by designing the area of their trapping layer without any external process, which is much beneficial to the low cost process fabrication of the memory array and driving circuits, since the memory and switch/digital transistors can be fabricated at the same time. Finally, the presented TFT memory exhibits a maximum memory window of 15 V, excellent fatigue and retention properties more than 30,000 s without any charge loss. The transparent floating gate memory with the ZnO charge-trap layer has great potential for application of 3D, transparent or multi-value memory.

A Machine Learning Attack Resilient True Random Number Generator Based on Stochastic Programming of Atomically Thin Transistors.

A true random number generator (TRNG) is a critical hardware component that has become increasingly important in the era of Internet of Things (IoT) and mobile computing for ensuring secure communication and authentication schemes. While recent years have seen an upsurge in TRNGs based on nanoscale materials and devices, their resilience against machine learning (ML) attacks remains unexamined. In this article, we demonstrate a ML attack resilient, low-power, and low-cost TRNG by exploiting stochastic programmability of floating gate (FG) field effect transistors (FETs) with atomically thin channel materials. The origin of stochasticity is attributed to the probabilistic nature of charge trapping and detrapping phenomena in the FG. Our TRNG also satisfies other requirements, which include high entropy, uniformity, uniqueness, and unclonability. Furthermore, the generated bit-streams pass NIST randomness tests without any postprocessing. Our findings are important in the context of hardware security for resource constrained IoT edge devices, which are becoming increasingly vulnerable to ML attacks.

Recharging process of commercial floating-gate MOS transistor in dosimetry application

We investigated the recharging process of commercial floating gate device (EPAD) during the six different dose rates and ten irradiation cycles with the highest dose rate. Dose rate dependence of the floating gate dosimeter was observed from 1 Gy/h to 26 Gy/h (H2O). There is no change of the dosimetric characteristic with a constant dose rate of 26 Gy/h for ten cycles. The absorbed dose does not affect the drift of the threshold voltage readings after the irradiation steps. The reprogramming characteristic is not degrading with the absorbed dose for the ten irradiation cycles, giving the promising potential in the application for dosimetric purposes.

A Versatile FG-MOSFET Inverter Design for X-Ray Radiation Dosimetry Applications.

A novel inverter-based digital floating-gate MOSFET sensor design for commercial X-ray dosimetry is presented. The biomedical healthcare industry sterilizes blood products for storage purposes using Gamma and X-ray radiations. This requires an ultra-low-power dosimeter that ensures irradiation does not exceed the maximum allowable 50 Gy while providing the required minimum levels of 25 Gy. In this work, minimum-sized MOS transistor devices are employed in an inverter configuration, eliminating the continuous flow of current and reducing power consumption significantly. Maximum measured currents, which flow only during the transition period, are in the nA range, compared to continuous currents of conventional sensor designs in the μA range. Final measured results show the viability of the proposed design for radiation dosimetry applications.

Demonstration of intrinsic STDP learning capability in all-2D multi-state MoS2 memory and its application in modelling neuromorphic speech recognition

The human brain can be characterized by its large number of adaptive synapses, connecting billions of neurons capable of both learning and perceiving the environment. Neuromorphic computing, based on brain-inspired principles, is a promising technology, to build low-power, distributed, fault-tolerant intelligent systems mainly for perception tasks. Here, we demonstrate the intrinsic capability of floating gate (FG) MoS2 device (MoS2 FG-FET) to model the spike time dependent plasticity (STDP) learning rule that is based on the transient response of the MoS2 channel to spikes applied to the source and gate leads. We implemented the STDP learning protocol in a neuromorphic speech recognition system (NSRS), inspired by the human auditory pathway, for various auditory recognition tasks. Our proposed NSRS consists of a cochlea model, an unsupervised feature learning stage, and a simple linear classifier. The unsupervised learning stage uses the biologically plausible STDP learning in novel two-dimensional MoS2 FG-FET memory which circumvents the requirement of any other learning circuitry. Demonstration of STDP modelling in two-dimensional (2D) MoS2 is an important step towards incorporating 2D architectures for reduced device footprints in neuromorphic learning circuits.

Analysing a common-source amplifier implemented with floating-gate transistors and coupled feedback loop

ABSTRACT The input stage of an operational or transconductance amplifier could be a common-source amplifier and it should be designed carefully, since it contributes in a significant way to the performance of the entire cell. In this document, we show the results of analysing a basic transconduction cell based on the multiple-input ffioating-gate transistor in a common-source amplifier configuration. A particular feature of the cell that we analyse is that it contains a feedback loop towards one of the coupled gates that serves to improve the linearity. This simple cell could be a input stage in more complex circuits. We present studies of linearity, gain, output resistance and distortion to be compared with an entirely MOS common-source amplifier. Experimental tests were conducted based on an implemented integrated circuit. In our comparison, we note that the cell based on the ffioating-gate transistor has a remarkable linearity in conditions in which the MOS version would not operate properly. In addition, we experimentally observe the phenomena predicted by the theory, such as gain and operation point manipulation, according to the values of the voltages at the other control gates. Thus, it is possible to improve the design of operational amplifiers, and other similar circuits, because they provide greater linearity and less distortion; however, we observed lower transconductance and an increase in the output resistance.

Dual-color charge-sensitive infrared phototransistors with dynamic optical gate

Infrared multispectral photodetectors with high performance show great potential in a broad range of applications. Here, sensitive and controllable dual-color photodetection at 10.6 and 15.7 μm is demonstrated by using a charge sensitive infrared phototransistor (CSIP) with dynamical optical gate. The CSIP device is fabricated in a GaAs/AlGaAs double quantum well (QW) crystal with both upper and lower QWs (7 and 11 nm thick, respectively) being photosensitive via intersubband absorption and, hence, each QW corresponding to one target wavelength (10.6 and 15.7 μm, respectively). Moreover, the upper QW serves as a photosensitive floating gate (FG), while the lower QW functions as the conducting channel of the phototransistor. By periodically lifting-up (lowering-down) the electrostatic potential of FG, the photoresponse at 10.6 (15.7 μm) associated with photoexcitation in upper (lower) QW can be achieved. This electrically controllable photoresponse together with intrinsically high photoconductive gain (∼102) provides a scheme to realize sensitive dual-color photodetection for infrared optoelectronic applications.