Floating-gate Research Articles

Three-Terminal Floating-Gate Cell for Threshold-Voltage Control of Organic Thin-Film Transistors

A floating-gate (FG) cell as a circuit-level approach to control the threshold voltage of organic thin-film transistors (TFTs) operated in the transdiode configuration is presented. Charging and discharging of the FG are achieved by controlling the charge leakage through the gate dielectric of one of the organic TFTs that constitute the FG cell. Using programming voltages not exceeding 4 V, systematic tuning of the threshold voltage to values between −0.5 and 2.6 V was achieved. The versatility of the concept is demonstrated by employing organic-TFT-based FG cells as transdiodes with programmable threshold voltage in passive rectifiers and diode-load inverters fabricated on flexible, transparent plastic substrates. Rectifiers with programmable FG cells show flatter frequency response, improved 3-dB point, and reduced ripple compared to conventional rectifiers. Inverters with programmable FG-transdiode load have larger small-signal gain, larger output-voltage swing, and larger noise margins than conventional diode-load inverters.

Balanced Multi-Cell Modulation for Flash Memory

The cell (i.e., the storage unit) in flash memory is a floating-gate MOSFET where data is stored in the form of trapped charge into its floating gate. The flash memory die is organized into blocks where each block consists of multiple wordlines that can be individually programmed. Each wordline consists of tens of thousands of cells and is organised into log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (q) pages where q is the number of threshold voltage levels a cell has. The pages are separately encoded to enable reading them individually. A key parameter of flash memory is its random read speed where small chunks of data are read from random addresses. The disparity in random read speed across pages can be minimized by using a balanced Gray labelling (BGL) to map the binary data into threshold voltages which allows reading different pages with almost the same number of sensing operations. We provide new BGL instances whereby multi-cell modulation (MCM) is used to map binary data into threshold voltages of multiple cells. The proposed modulations are found through computer search routines and are shown to improve the flash memory reliability via numerical simulations.

Engineering an Indium Selenide van der Waals Interface for Multilevel Charge Storage.

As the continuous miniaturization of floating-gate transistors approaches a physical limit, new innovations in device architectures, working principles, and device materials are in high demand. This study demonstrated a nonvolatile memory structure with multilevel data storage that features a van der Waals gate architecture made up of a partially oxidized surface layer/indium selenide (InSe) van der Waals interface. The key functionality of this proof-of-concept device is provided through the generation of charge-trapping sites via an indirect oxygen plasma treatment on the InSe surface layer. In contrast to floating-gate nonvolatile memory, these sites have the ability to retain charge without the help of a gate dielectric. Together with the layered structure, the surface layer with charge-trapping sites facilitates continual electrostatic doping in the underlying InSe layers. The van der Waals gating effect is further supported by trapped charge-induced core-level energy shifts and relative work function variations obtained from operando scanning X-ray photoelectron spectroscopy and Kelvin probe microscopy, respectively. On modulating the amount of electric field-induced trapped electrons by the electrostatic gate potential, eight distinct storage states remained over 3000 s. Moreover, the device exhibits a high current switching ratio of 106 within 11 cycles. The demonstrated characteristics suggest that the engineering of an InSe interface has potential applications for nonvolatile memory.

Continuous-Time Programming of Floating-Gate Transistors for Nonvolatile Analog Memory Arrays

Floating-gate (FG) transistors are a primary means of providing nonvolatile digital memory in standard CMOS processes, but they are also key enablers for large-scale programmable analog systems, as well. Such programmable analog systems are often designed for battery-powered and resource-constrained applications, which require the memory cells to program quickly and with low infrastructural overhead. To meet these needs, we present a four-transistor analog floating-gate memory cell that offers both voltage and current outputs and has linear programming characteristics. Furthermore, we present a simple programming circuit that forces the memory cell to converge to targets with 13.0 bit resolution. Finally, we demonstrate how to use the FG memory cell and the programmer circuit in array configurations. We show how to program an array in either a serial or parallel fashion and demonstrate the effectiveness of the array programming with an application of a bandpass filter array.

Thin film transistors integrating CsPbBr3 quantum dots for optoelectronic memory application

All-inorganic perovskite cesium lead bromide (CsPbBr3) quantum dots (QDs) have been used as charge storage centers in floating-gate transistors. In this work, CsPbBr3 QDs are integrated into thin film transistors to create transistor-based memory. Unlike the floating-gate transistors previously reported, the CsPbBr3 QDs are placed between the dielectric and semiconductor layer, leading to direct contact with the semiconductor layer. Characterization of the device performance reveals that the CsPbBr3 QDs exhibit a strong tendency to store holes instead of electrons. Analysis unravels that this property possibly comes from the junction formed between the CsPbBr3 QDs and the transistor’s semiconductor layer, which can facilitate hole injection from the semiconductor layer to the QDs under a negative gate bias, as well as the storage of the injected holes in the QDs. Devices using an organic semiconductor (P3HT) or two-dimensional material (graphene) consistently verify this speculation. Benefiting from the hole storage ability of the CsPbBr3 QDs, these devices show a benign non-volatile memory feature. As transistor-based memories, these devices can be programmed by electricity and erased by electricity or light illumination, rendering them as capable of optoelectronic memory application. This work offers an alternative approach for novel transistor-based optoelectronic memory.

Cryogenic Floating-Gate CMOS Circuits for Quantum Control

Voltage biases are often required to bias Qubits, and yet applying a static bias requires separate chip wires, dramatically increasing the system complexity. An ideal approach would be having a nonvolatile digital or analog memory to avoid these issues. This article shows floating-gate (FG) structures could be used to set and forget potentials and tunnel barrier tuning as well as enable memory applications. It reports FG measurements at cryogenic temperatures (T = 4 K), enabling reprogrammable FG devices in cryogenic environments. Using a multipurpose FG test structure, measurements show the FG device and circuit operation as well as charge programming measurements based on electron tunneling and hot-electron injection at T = 4 K and T = 300 K. These results open applications in classical cryogenic computing, controlling quantum computation, and other cryogenic temperature applications.

Gain Boosted Folded Cascode Op-Amp with Capacitor Coupled Auxiliary Amplifiers

A novel gain boosted folded cascode Op-Amp using simple single stage auxiliary amplifiers is presented. The proposed auxiliary amplifiers are designed in a way that have proper input and output DC common mode voltage without using common mode feedback network. The inputs of the auxiliary amplifiers are insulated by the coupling capacitors and floating-gate MOS transistors. Thus, the DC input voltage level limit has been removed. Diode connected transistors are also used in the output of the auxiliary amplifiers, which keep the output voltage level at the desired. A simple single stage auxiliary amplifier imposes fewer poles and zeroes on the main amplifier compared to more complicated amplifiers where consumes also less power consumption. Simulation results in a 0.18μm CMOS technology show a DC gain enhancement of about 20dB while output swing, slew rate, settling time, phase margin and gain-bandwidth retain almost as the same as previous folded cascode design.

Low Voltage Quasi Floating Gate Current Mirror with Improved Output Impedance

Low Voltage Quasi Floating Gate Current Mirror with Improved Output Impedance

Floating-gate photosensitive synaptic transistors with tunable functions for neuromorphic computing

Synaptic devices that merge memory and processing functions into one unit have broad application potentials in neuromorphic computing, soft robots, and human-machine interfaces. However, most previously reported synaptic devices exhibit fixed performance once been fabricated, which limits their application in diverse scenarios. Here, we report floating-gate photosensitive synaptic transistors with charge-trapping perovskite quantum dots (PQDs) and atomic layer deposited (ALD) Al2O3 tunneling layers, which exhibit typical synaptic behaviors including excitatory postsynaptic current (EPSC), pair-pulse facilitation and dynamic filtering characteristics under both electrical or optical signal stimulation. Further, the combination of the high-quality Al2O3 tuning layer and highly photosensitive PQDs charge-trapping layer provides the devices with extensively tunable synaptic performance under optical and electrical co-modulation. Applying light during electrical modulation can significantly improve both the synaptic weight changes and the non-linearity of weight updates, while the memory effect under light modulation can be obviously adjusted by the gate voltage. The pattern learning and forgetting processes for “0” and “1” with different synaptic weights and memory times are further demonstrated in the device array. Overall, this work provides synaptic devices with tunable functions for building complex and robust artificial neural networks.

Total Gain Recovery in Floating Gate Thin-Film Transistors for Neuromorphic and Edge Computing

We propose a floating-gate (FG) thin-film transistor architecture which alleviates a significant limitation present since the inception of FG field-effect transistors, namely the loss of gain due to parasitic capacitive coupling on the FG [1].The interest in large area electronics has grown beyond traditional applications, such as display and sensing arrays, with recent trends including neuromorphic and edge computing. However, the challenges of fabricating robust thin film transistor (TFT) circuits have remained despite the many significant achievements in material systems and process development. In order to realise the full benefit of low-cost, high-throughput manufacturing methods, device shortcomings need to be addressed [2]. In FG devices, specifically, one major limitation is the degradation of gain compared to conventional devices, as a result of capacitive coupling of the channel and drain potentials to the floating gate. The problem is far more severe in contact-controlled TFTs, such as the staggered-electrode, high-gain source-gated transistor (SGT) [3, 4], and crippling in conventional TFTs manufactured in materials such as InGaZnO [5].SGT operation differs from conventional field-effect TFTs, whereby the semiconductor is fully depleted at the source edge by an energy barrier (e.g. Schottky), which is reverse biased by the application of drain voltage. Charge injection is modulated via the gate/source overlap, producing very low saturation voltage and ultra-low output conductance gd [3]. This latter feature yields the distinctive and extremely high intrinsic gain observed in such devices. A large voltage drop occurs across the source depletion region, producing the notable early saturation and, consequently, the channel potential is maintained at a value close to the drain potential for operating conditions in which a conventional TFT would still be working in the linear region. As such, when a floating gate is used in a SGT, the FG couples strongly to both the drain and the channel. FG potential varies considerably with drain voltage, thus increasing charge injection along the source, ultimately raising gd . While gd is still orders of magnitude lower than that of a TFT or FG TFT (see Figure 1), many analog applications would benefit from a solution to this problem [1].Here, we present a staggered-electrode contact-controlled device, the multimodal transistor (MMT), which shares SGT charge injection principles, however the switching mechanism of its channel is controlled by a separate gate [6]. In a FG MMT, the source gate responsible for charge injection and channel switching gate are designed as FGs (FG1 and FG2, respectively) and a main control gate (CG) may overlap both FGs. FG MMTs have been fabricated in low T°C technology [6] with Ni source and drain contacts. ICP-CVD (Inductively Coupled Plasma Chemical Vapour Deposition) via the Corial 210D reactor was used to deposit µ-Si as active layer, as well as the insulators of the gate stack (Figure 1a). Temperature never exceeded 250°C in any of the processing steps.The MMT exhibits the same high-gain properties of the SGT and preserves it even in FG configuration. With the channel and drain potentials coupling to FG2, its potential is raised significantly higher than FG1 (see Figures 1b and 1c for TCAD simulation with Silvaco Atlas), which is effectively shielded. As charge injection is exclusively modulated by FG1, the low saturation and extremely low gd are maintained, in contrast to the FG SGT (see Figure 1c). Thus, extremely high gain can be obtained from the FG MMT structure, with a wide range of applicability to traditional analog applications such as displays and sensors, as well as emerging neuromorphic circuits.Figure. 1 a) Photomicrograph of a µ-Si floating gate MMT (FG MMT); b) FG2 potential is significantly raised, while FG1 is shielded from parasitic capacitive coupling from the channel and drain potential, keeping charge injection at the source constant with drain voltage. c) Output conductance gd comparison confirms FG MMT gd is significantly lower than that of the equivalent FG SGT.

Linearity Improvement of Bulk Driven Floating Gate OTA Using Cross-Bulk and Quasi-Bulk Techniques

In this paper, two highly linear OTAs are presented using a combination of three linearization techniques: floating gate, bulk driven, and source degeneration. In the first OTA, bulk driven floating gate MOSFETs are used as input transistors. The input signal given at the bulk terminals of these input transistors are in the opposite phase of the input signal provided to one of the gates of the respective floating gate MOSFET. This cross-coupling method resulted in a highly linear voltage-to-current conversion at the cost of reduced transconductance. In the second proposed OTA, this reduction in transconductance is restored by using novel quasi-bulk floating gate MOSFETs as input transistors while maintaining the improved linearity. Both the OTAs are designed and simulated using 180 nm CMOS design library and powered with [Formula: see text]0.5[Formula: see text]V dual power supply. The process variation and mismatch effects on both the OTAs are examined using corner and Monte Carlo analysis. The layouts of the proposed OTAs are also presented and workability is confirmed using post-layout simulations.

Logic-in-memory based on an atomically thin semiconductor

The growing importance of applications based on machine learning is driving the need to develop dedicated, energy-efficient electronic hardware. Compared with von-Neumann architectures, brain-inspired in-memory computing uses the same basic device structure for logic operations and data storage1–3, thus promising to reduce the energy cost of data-centric computing significantly4. While there is ample research focused on exploring new device architectures, the engineering of material platforms suitable for such device designs remains a challenge. Two-dimensional materials5,6 such as semiconducting MoS2 could stand out as a promising candidate to face this obstacle thanks to their exceptional electrical and mechanical properties7–9. Here, we explore large-area grown MoS2 as an active channel material for developing logic-in-memory devices and circuits based on floating-gate field-effect transistors (FGFET). The conductance of our FGFETs can be precisely and continuously tuned, allowing us to use them as building blocks for reconfigurable logic circuits where logic operations can be directly performed using the memory elements. After demonstrating a programmable NOR gate, we show that this design can be simply extended to implement more complex programmable logic and functionally complete sets of functions. Our findings highlight the potential of atomically thin semiconductors for the development of next-generation low-power electronics.

Exploiting Error Characteristic to Optimize Read Voltage for 3-D NAND Flash Memory

3-D NAND flash memory has become increasingly popular nonvolatile storage devices due to large capacity and high performance. With the increase of program/erase (P/E) cycles and retention periods, the threshold voltage distribution of 3-D NAND flash memory is prone to shift such that it is difficult to accurately obtain the read reference voltage (RRV). When reading data, read retry operations perform multiple flash sensing to read bit information correctly, inducing extended read latency. To mitigate the read latency, a method of precisely acquiring the RRV is urgently needed. Using an field-programmable gate array (FPGA) hardware testing platform, this article first studies error characteristics of 3-D triple-level cell (TLC) NAND flash memory with the floating gate (FG) structure, which includes the variations of raw bit error rates (RBERs) in different layers and pages, the variations of block reads under different read modes, and the threshold voltage shifting characteristic. Then, based on these characterizations, this article develops an error characteristic aware RRV acquisition scheme, called ECRRV, to gain optimal RRV by exploiting the least square method. Experimental results show that the proposed scheme can significantly diminish the RBER and block read count.

Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate Voltage.

The memory window of floating gate (FG) type non-volatile memory (NVM) devices is a fundamental figure of merit used not only to evaluate the performance, such as retention and endurance, but also to discuss the feasibility of advanced functional memory devices. However, the memory window of 2D materials based NVM devices is historically determined from round sweep transfer curves, while that of conventional Si NVM devices is determined from high and low threshold voltages (Vth s), which are measured by single sweep transfer curves. Here, it is elucidated that the memory window of 2D NVM devices determined from round sweep transfer curves is overestimated compared with that determined from single sweep transfer curves. The floating gate voltage measurement proposed in this study clarifies that the Vth s in round sweep are controlled not only by the number of charges stored in floating gate but also by capacitive coupling between floating gate and back gate. The present finding on the overestimation of memory window enables to appropriately evaluate the potential of 2D NVM devices.

Managing Device Lifecycle: Reconfigurable Constrained Codes for M/T/Q/P-LC Flash Memories

Flash memory devices are winning the competition for storage density against magnetic recording devices. This outcome results from advances in physics that allow storage of more than one bit per cell, coupled with advances in signal processing that reduce the effect of physical instabilities. Constrained codes are used in storage to avoid problematic patterns. Recently, we introduced binary symmetric lexicographically-ordered constrained codes (LOCO codes) for data storage and data transmission. This paper introduces simple constrained codes that support non-binary physical substrates; multi, triple, quad, and the currently-in-development penta-level cell (M/T/Q/P-LC) Flash memories. The new codes can be easily modified if problematic patterns change with time. These codes are designed to mitigate inter-cell interference, which is a critical source of error in Flash devices. The occurrence of errors is a consequence of parasitic capacitances in and across floating gate transistors, resulting in charge propagation from cells being programmed to the highest charge level to neighboring cells being programmed to lower levels. The new codes are called $q$-ary asymmetric LOCO codes (QA-LOCO codes), and the construction subsumes codes previously designed for single-level cell (SLC) Flash devices (A-LOCO codes). QA-LOCO codes work for a Flash device with any number, $q$, of levels per cell. For $q \geq 4$, we show that QA-LOCO codes can achieve rates greater than $0.95 \log_2 q$ information bits per coded symbol. The complexity of encoding and decoding is modest, and reconfiguring a code is as easy as reprogramming an adder. Capacity-achieving rates, affordable encoding-decoding complexity, and ease of reconfigurability support the growing development of M/T/Q/P-LC Flash memory devices, as well as lifecycle management as the characteristics of these devices change with time.

Design, modelling, and simulation of a floating gate transistor with a novel security feature

This study proposes a new generation of floating gate transistors (FGT) with a novel built-in security feature. The new device has applications in guarding the IC chips against the current reverse engineering techniques, including scanning capacitance microscopy (SCM). The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate, even in nano-meter scales. The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate. This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic. Furthermore, this model was verified with a simulation. In addition, the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor. The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated. Finally, the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.

NrGO Floating Gate/SiOXNY Tunneling Layer Stack for Nonvolatile Flash Memory Applications

This paper presents an ultra–thin silicon oxynitride (SiOXNY, 4 nm) tunneling layer, nitrogen functionalized reduced graphene oxide (NrGO, 3–5 layer) floating gate (FG) and poly (methyl methacrylate) (PMMA, 60 nm) blocking layers based Al/PMMA/NrGO/SiOXNY/p–Si/Au, non–volatile flash memory (NVFM) structures. The ultra–thin SiOXNYhelps in improving the interface with Si, resulting in lower gate leakage current density and considerable enhanced retention characteristics. The nitrogen engineered GO followed by reduction to NrGO under UV illumination attributes to the modification of the physiochemical properties, hence beneficial for non-volatile memory applications. The uniform, stress free and low temperature processing advocates the potential of PMMA as blocking layer for improved memory characteristics. The electrical characterizations on the fabricated Al/PMMA/NrGO/SiOXNY/p–Si/Au gate stack demonstrates a memory window ( ${\delta }\text{W}$ ) of ~1.25 V @ ± 3 V and ~2.6 V @ ± 5 V, low gate leakage current density (J) ~10 nA/cm2@ −1 V, retention $\sim 3 \times 10^{11}$ sec (> 10 years with extrapolation) and endurance of more than 100 cycles.

Nonvolatile Multilevel Photomemory Based on Lead-Free Double Perovskite Cs2AgBiBr6 Nanocrystals Wrapped Within SiO2 as a Charge Trapping Layer.

Floating gate transistor photomemory (FGTPM) has been regarded as one of the most prospective nonvolatile photomemory devices because of its compatibility with transistor-based circuits, nondestructive reading, and multilevel storage. Until now, owing to the excellent photoelectric properties, lead-based perovskite nanocrystals (PNCs) have been applied in most of the perovskite-based FGTPM devices and embedded in the polymer matrix as the charge trapping layer. However, the polymer matrix and its solvent would degrade the structure of the PNCs, resulting in the loss of their unique photoresponse ability. In addition, lead-based perovskites have environmental unfriendliness and poor stability. Hence, a novel nonvolatile FGTPM based on oligomeric silica (OS) wrapped lead-free double perovskite Cs2AgBiBr6 NCs was demonstrated for the first time. Acting synchronously as the protection layer for the discrete Cs2AgBiBr6 NCs and charge tunneling layer for the FGTPM device, the OS layer can achieve controllable thickness by adjusting the process parameters, leading to an adjustment of storage properties with a larger memory window (58 V). Owing to the excellent photoresponse ability of the Cs2AgBiBr6@OS composite layer, the FGTPM device exhibited high-performance with repeatable multilevel nonvolatile photomemory and precise photoresponse ability of wavelength/time/power-dependent photoirradiation without extra gate biasing.

Laser‐Assisted Multilevel Non‐Volatile Memory Device Based on 2D van‐der‐Waals Few‐Layer‐ReS2/h‐BN/Graphene Heterostructures

AbstractFew‐layer rhenium disulfide (ReS2) field‐effect transistors with a local floating gate (FG) of monolayer graphene separated by a thin hexagonal boron nitride tunnel layer for application to a non‐volatile memory (NVM) device are designed and investigated. FG‐NVM devices based on two‐dimensional van‐der‐Waals heterostructures have been recently studied as important components to realize digital electronics and multifunctional memory applications. Direct bandgap multilayer ReS2 satisfies various requirements as a channel material for electronic devices as well as being a strong light‐absorbing layer, which makes it possible to realize light‐assisted optoelectronic applications. The NVM operation with a high ON/OFF current ratio, a large memory window, good endurance (&gt;1000 cycles), and stable retention (&gt;104 s) are observed. The successive program and erase states using 10 ms gate pulses of +10 V and −10 V are demonstrated, respectively. Laser pulses along with electrostatic gate pulses provide multibit level memory access via opto‐electrostatic coupling. The devices exhibit the dual functionality of a conventional electronic memory and can store laser‐pulse excited signal information for future all‐optical logic and quantum information processing.

Improving Performance of Nonvolatile Perovskite‐Based Photomemory by Size Restrain of Perovskites Nanocrystals in the Hybrid Floating Gate

AbstractPerovskite‐based photomemory adopting a floating‐gate architecture recently attracts research attention for developing efficient photo‐recording devices due to its simplified structure and non‐contact light‐programming feature. Herein, the memory characteristics of such type device is improved by the precise control of the size of perovskite nanocrystals (NCs) in the hybrid floating gate. Compared to the previous case of using polystyrene (PS) as the host polymer matrix, a N‐containing polymer, poly(2‐vinyl pyridine) (P2VP), is revealed to better regulate the size of embedded perovskite NCs into the nanometer level (7–9 nm) owing to the intense coordination between the N atom in P2VP and the Pb2+ ions of perovskite through Lewis acid‐base interaction. As benefitting from the reduced current dissipation and interfacial charge recombination at the gate/channel interface, the P2VP‐derived photomemory not only delivers a much higher On/Off current ratio (105) than the value (103) of the reference PS‐based device but also requires a much shorter illumination time (5 s) and low drain voltage (‐1 V) to achieve decent photo‐recording function. Besides, it possesses good long‐term retention for 104 s, excellent stress endurance over 100 cycles, and respectable ambient stability over 6 months due to the well isolation of perovskite NCs in the P2VP matrix.