Cryogenic Floating-Gate CMOS Circuits for Quantum Control

Jennifer Hasler,David Reilly,Kushal Das,Neil Dick,Alireza Moini,Brian Degnan

doi:10.1109/tqe.2021.3067996

Abstract

Voltage biases are often required to bias Qubits, and yet applying a static bias requires separate chip wires, dramatically increasing the system complexity. An ideal approach would be having a nonvolatile digital or analog memory to avoid these issues. This article shows floating-gate (FG) structures could be used to set and forget potentials and tunnel barrier tuning as well as enable memory applications. It reports FG measurements at cryogenic temperatures (T = 4 K), enabling reprogrammable FG devices in cryogenic environments. Using a multipurpose FG test structure, measurements show the FG device and circuit operation as well as charge programming measurements based on electron tunneling and hot-electron injection at T = 4 K and T = 300 K. These results open applications in classical cryogenic computing, controlling quantum computation, and other cryogenic temperature applications.

Highlights

Qubits in condensed matter systems typically require gate electrodes to tune chemical potentials and compensate for offset charges
The charge programming is based on electron tunneling (Section III), as well as hot-electron injection (Section IV), device mechanisms that are predictable at T = 4 K and 300 K
Electron tunneling and hot-electron injection mechanisms enable predictable charge programming at 4 K and 300 K. These measurements are just the start of the possible measurements at cryogenic temperatures that include transistor channel, transistor well, and hot-electron injection measurements systematically measured across a range of temperatures, a range of drain-to-source voltages, and a wider range of channel currents

Summary

FG CHARACTERIZATION STRUCTURE

The integrated circuit (IC) is bonded directly to a PCB that is placed in the cryo-temperature chamber. Hot-electron injection is enabled by turning off the amplifier’s local power supply (disabling the amplifier), biasing the source and drain voltages at Vdd and GND, respectively, while fixing the voltage applied to the capacitors (Vtun = 5 V, C1 = C2 to see a slightly above-threshold current) connected to the FG node. In this setup, hot-electron injection is characterized through a single MOSFET transistor monitored by measuring its drain current. Disabling the amplifier enables measuring hot-electron injection from a single pFET transistor, as the pFET input transistor shows hotelectron injection into the FG node (4 K and 300 K) These measurements performed hot-electron injection through a MOSFET operating with saturated above-threshold channel currents (Is). These trajectories of Is versus time can be extracted to find Iinj versus Is, as previously discussed at 300K [35], [37], when the voltage difference magnitude between the source and drain voltages is 5 V

MOSFET CHANNEL CURRENT MODELING AS PART OF HOT-ELECTRON INJECTION PHYSICS

Findings

Is dIs dt