Floating-gate MOS Transistors Research Articles

A design TCADAS tool for semiconductor devices and case study of 65 nm conventional floating-gate MOS transistor

An automatic programming tool has become an essential component in virtual fabrication in recent years. This paper aims to propose a methodology of virtual fabrication for semiconductor devices and design a tool called Technology Computer-Aided Design Automatic Simulation (TCADAS) which can perform a completely virtual fabrication, device simulation, process variation, and output extraction. Especially, the TCADAS tool eliminates drudgery when studying semiconductor devices such as complexity in setting inputs, substantial manual work, and long run time of simulations. This work investigates the completed flow for a 65 nm conventional Floating-gate MOS transistor as a case study, which is widely considered a vital determinant of the non-volatile memory field. A detailed automatic process from the entry to a completed three-dimension structure, device characterization, extract important output parameters such as memory window, ION/IOFF, Gate Coupling Ratio (GCR), and speed operations are presented. The TCADAS tool was designed by Python language and the utilities of TCAD Silvaco tools including Athena, Atlas, and DevEdit3D.

A simulated fabrication and characterization of a 65 nm floating-gate MOS transistor☆

The aim of this study was to virtual fabricate and characterize a Floating-gate MOS transistor of the 65 nm process. The fabrication process was designed and characterized using the TCAD Silvaco tools. In our work, a detailed flow and the parameters are proposed to virtual fabricate the complete Floating-gate MOS transistor, which has extraordinary performances. The MOS has a large timing window of 4 V, a high gate capacitance ratio parameter of 0.645, and a high Write/Erase speed of 50 ms/70 ms. Interestingly, the results are obtained with a thin thickness of 9 nm of a tunnel oxide layer which is smaller than such layer in other works and low supply voltages in which the control gate, drain, and source voltage values are ± 6 V, 1 V, and 1 V, respectively. In addition, our paper presents the effect of the control gate voltage on the performance of the device when it increases from 6 V to 18 V.

Low Voltage-Low Power Wide Range FGMOS Fully Differential Difference Current Conveyor And Application Examples

ABSTRACT A novel floating gate MOS (FGMOS) low voltage-low power wide range fully differential difference current conveyor (FDDCCII) is proposed. Proposed FDDCCII has a power consumption of 375nW and a rail-to-rail input signal range. Appropriate selection of the ratio between total capacitance vs. input capacitance of FGMOS transistors leads to a decrease in the transconductance and this feature increases the input signal oscillation range of the FDDCCII. Some of the key properties of the proposed FDDCCII are the bandwidth of 31 Mhz and 26 MHz at current conveying curve and voltage conveying curve, respectively.

A Novel Domino Logic Based on Floating-Gate MOS Transistors

Domino logic finds a wide variety of applications in both static and dynamic random-access memories and in high-speed microprocessors. However, the main limitation of the domino logic-circuit family is the trade-off between the noise immunity and speed. In order to resolve such a trade-off, this paper proposes a domino logic that is based on floating-gate MOS (FGMOS) transistors. Compact-form expressions are derived for the noise margins for the low and high inputs as well as the propagation delays. The proposed scheme is verified by simulation adopting the 45 nm CMOS predictive technology model (PTM) with a power-supply voltage of 1 V. The obtained results unveil that the proposed domino logic outperforms the conventional domino logic in terms of the power-delay product and the energy-delay product when realizing wide fan-in OR gates. The realized, with the proposed scheme, 16-input OR gate has an average power consumption of 3.7 µW and a propagation delay of 51 ps.

The DIME-1 Experiment Flown as Part of NASA’s SET-1 Project on the DSX Satellite

Dosimetry Intercomparison and Miniaturization Experiment (DIME-1) is an experiment flying as part of NASA’s Space Experimental Testbed (SET-1) satellite project on the Air Force’s Demonstration and Science Experiments (DSX) satellite to compare novel dosimeters with the standard radiation field-effect transistor (RadFET) dosimeters. It consists of five operational RadFETs under different thicknesses of hemispherical Al and Ta shields and three commercial-off-the-shelf (COTS) floating-gate MOS transistor (FGMOS) UV Proms programmed as dosimeters. The flight path crosses the entire slot region and cuts the Van Allen belts on each 5.25-h orbit of the Earth. The dosimeters on DIME-1 and its sister board DIME-2, consisting of two linear energy transfer (LET) spectrometers, are capable of measuring total ionizing dose (TID) and single-event effects (SEEs) which are responsible for degrading or causing catastrophic failure of electronic circuits in space. Results comparing the different dosimeters with the standard RadFET devices are shown to be in quite good agreement in terms of the shape of the total dose versus time plots over the 1.75 year life of the DSX mission but not in agreement over the TID measured presumably due to short-range protons reaching the sensitive volume of FGMOS devices but not reaching that of RadFETs. DIME-1 traveled into a radiation environment that well-designed circuits, flown during solar minimum, will survive.

Recharging process of commercial floating-gate MOS transistor in dosimetry application

We investigated the recharging process of commercial floating gate device (EPAD) during the six different dose rates and ten irradiation cycles with the highest dose rate. Dose rate dependence of the floating gate dosimeter was observed from 1 Gy/h to 26 Gy/h (H2O). There is no change of the dosimetric characteristic with a constant dose rate of 26 Gy/h for ten cycles. The absorbed dose does not affect the drift of the threshold voltage readings after the irradiation steps. The reprogramming characteristic is not degrading with the absorbed dose for the ten irradiation cycles, giving the promising potential in the application for dosimetric purposes.

Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS

With technology scaling, stability, power dissipation, and device variability, the impact of process, voltage and temperature (PVT) variations has become dominant for static random access memory (SRAM) analysis for productivity and failure. In this paper, ten-transistors (10T) and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors (FGMOS). Power centric parameters viz. read power, write power, hold power and delay are the performance analysis metrics. Further, the stochastic parameter variation to study the variability tolerance of the redesigned cell, PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell. Stability has been illustrated with the conventional butterfly method giving read static noise margin (RSNM) and write static noise margin (WSNM) metrics for read stability and write ability, respectively. A comparative analysis with standard six-transistor SRAM cell is carried out. HSPICE simulative analysis has been carried out for 32[Formula: see text]nm technology node. The redesigned FGMOS SRAM cells provide improved performance. Also, these are robust and reliability efficient with comparable stability.

Gain Boosted Folded Cascode Op-Amp with Capacitor Coupled Auxiliary Amplifiers

A novel gain boosted folded cascode Op-Amp using simple single stage auxiliary amplifiers is presented. The proposed auxiliary amplifiers are designed in a way that have proper input and output DC common mode voltage without using common mode feedback network. The inputs of the auxiliary amplifiers are insulated by the coupling capacitors and floating-gate MOS transistors. Thus, the DC input voltage level limit has been removed. Diode connected transistors are also used in the output of the auxiliary amplifiers, which keep the output voltage level at the desired. A simple single stage auxiliary amplifier imposes fewer poles and zeroes on the main amplifier compared to more complicated amplifiers where consumes also less power consumption. Simulation results in a 0.18μm CMOS technology show a DC gain enhancement of about 20dB while output swing, slew rate, settling time, phase margin and gain-bandwidth retain almost as the same as previous folded cascode design.

Floating-Gate MOS Transistor with Dynamic Biasing as a Radiation Sensor.

This paper describes the possibility of using an Electrically Programmable Analog Device (EPAD) as a gamma radiation sensor. Zero-biased EPAD has the lowest fading and the highest sensitivity in the 300 Gy dose range. Dynamic bias of the control gate during irradiation was presented for the first time; this method achieved higher sensitivity compared to static-biased EPADs and better linear dependence. Due to the degradation of the transfer characteristics of EPAD during irradiation, a function of the safe operation area has been found that determines the maximum voltage at the control gate for the desired dose, which will not lead to degradation of the transistor. Using an energy band diagram, it was explained why the zero-biased EPAD has higher sensitivity than the static-biased EPAD.

Sensing system with an artificial neural network based on floating-gate metal oxide semiconductor transistors

This paper shows a novel design of a gas sensor system based on artificial neural networks and Floating-gate MOS Transistors (FGMOS). Two types of circuits with FGMOS transistors of minimum dimensions were designed and simulated by Simulink of Matlab; simulations and experimental measurements results were compared obtaining good expectations. The reason of using FGMOS is that ANN can also be implemented with these kinds of devices, since ANN’s based on FGMOS are able to produce pseudo Gaussian-functions. These functions give a reliable option to determine the gas concentration. A sensitive thin film can be deposited on the FGMOS’s floating gate, which produces a charge variation due to the chemical reaction between the sensitive layer and the gas species, modifying the threshold voltage thereby a correlation of drain current of the FGMOS with gas concentration can be obtained. Therefore, a generator circuit was implemented for the pseudo Gaussian signal with FGMOS. This system can be applied in environments with dangerous species such as CO2, CO, methane, propane, among others. Simulations demonstrated that the implemented proposal has a good performance as an alternative method for sensing gas concentrations, compared with conventional sensors.

A New FGMOS UCCII and SIMO Type Universal Filter Application

DOI: 10.26650/electrica.2019.19006 A new floating gate MOS (FGMOS) universal current conveyor (UCCII) is proposed to have the properties of simplifier circuit topology, simpler signal processing and wider input swing. Since the FGMOS transistors are used in the proposed UCCII circuit, the number of transistors is reduced and the topology of the circuit is simplified because it is easier to get arithmetic operations in circuits by using FGMOS transistors when compared to conventional MOS transistors. At the same time, using FGMOS differential amplifier structure in the input stage of the FGMOS UCCII circuit increased the input signal swing resulting both an increase in the linearity of the circuit and an improvement in the voltage following properties. A single input multi output (SIMO) type universal filter application is given to show the versatility of the UCCII block. Both the proposed FGMOS UCCII circuit and filter circuit are simulated with SPICE program by using 0.35µm technology parameters. When the simulation results are analyzed it is seen that that the FGMOS UCCII circuit reached the expected improvements according to the MOS equivalent circuit and expected to be used in linearly tunable filters. Cite this article as : Keles S, Keles F, Kuntman HH. A New FGMOS UCCII and SIMO Type Universal Filter Application. Electrica 2019; 10.26650/electrica.2019.19006.

Validation of a CMOS-MEMS accelerometer based on FGMOS transduction by electromechanical modification of its coupling coefficient

This paper presents the design and fabrication of an accelerometer prototype through a CMOS silicon foundry with a technology able to deliver a floating-gate MOS transistor (FGMOS). The design of this device included a comb drive capacitor, with aluminum as the structural layer, in order to transform the FGMOS in an inertial sensor and its performance was evaluated electromechanically modifying the coupling coefficient of this FGMOS. A post-process micromachining step was added after the IC chip was received from the foundry. The case here described consists on a surface micromachining step such that the structural layer—aluminum in the case here reported—can be completely released making available a variable coupling capacitor (with air as dielectric) having free movement from which a variable coupling coefficient can be established. The results of a dynamic analysis applied to the resulting CMOS-MEMS structure are shown, demonstrating that this approach is interesting and promisorious as an option for inertial sensors.

Surface micromachining of a micro electromechanical inertial transducer based on commercially available Floating Gate Transistor technology

This work presents the results of different surface micromachining processes done on a chip from On Semiconductor 0.5 µm commercially available CMOS technology. The intended objective is to fabricate a MEMS inertial transducer in a monolithic substrate, as the electronics for signal processing are based on a Floating Gate MOS transistor, fully integrated in the electromechanical structure. According to the available layers and design rules from the foundry, an inertial sensor chip was designed and fabricated, except the last post–processing step, i.e., the removal of the sacrificial layer and thus releasing the inertial structure based on a surface micromachining process, allowing the completed device to behave as designed.

Low Power and Low Complexity Flip-Flop Design using MIFGMOS

Sequential logic is essential in many applications as data processing for speech recognition in cochlear implants. In this paper, a family of latches based on floating-gate MOS (FGMOS) transistors is presented. This family takes advantage on the fact that FGMOS logics process data using mostly passive devices, achieving small area and low-power, requirements of modern electronics. Post-layout SPICE simulations from an ON-Semiconductors 0.5 µm CMOS process technology shows improvements over conventional CMOS logic families, making FGMOS latches ideal for low-power applications.

Square root circuit using FGMOS translinear principle

A novel square root circuit using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. FGMOS transistors are being utilized in a number of new and exciting analog applications. These devices are available in standard CMOS technology because they are being widely used in digital circuits. FGMOS structures are also known as multi-input MOS and their multi input advantages make it simpler to realize an arithmetic signal processing circuit. Thus floating gate devices are now finding wider applications by analog researchers. The FGMOS drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only four FGMOS transistors in proposed square-root circuit. The main feature of this remarkably simple square root circuit is to reduce the errors generated by the second order effects in the current mode circuits employing translinear loop.

Low power FGMOS-based four-quadrant current multiplier circuits

In this paper, low-power, high-speed four-quadrant analog multiplier circuits have been presented, based on simple current squarer circuits. The squarer circuits consist of a floating-gate MOS transistor, operating in saturation region plus a resistor. These multipliers have a unique property of greatly reduced power as they do not have any bias currents. For performance evaluation, the designs are simulated using HSPICE software in 0.18 µm (level-49 parameters) TSMC CMOS technology. Using ± 0.5 V DC supply voltages for the first design, the simulation resulted in a maximum linearity error of 0.8%, the − 3 dB bandwidth of 635 MHz, the Total Harmonic Distortion of 0.57% (at 1 MHz), and maximum and static power consumption of 40.4 and 5.75 µW, respectively. Corresponding values for the second design with 1 V DC supply voltage are 0.4%, 394.8 MHz, 0.72%, 44 and 11.4 µW, respectively. Furthermore, in order to verify the robustness and reliability of the proposed works, Monte Carlo analysis are performed. For the mentioned analysis, 5% variations in channel width and length, gate oxide thickness and threshold voltage of all transistors and resistance values are considered.

Inertial sensing MEMS device using a floating-gate MOS transistor as transducer by means of modifying the capacitance associated to the floating gate

In this work, a novel application of floating gate MOS transistors is presented. An inertial sensor with an embedded FGMOS was designed, simulated and fabricated using commercially available CMOS technology, like the ON Semiconductor 0.5 µm, two poly, three metal, N-well, post-processed using a surface micromachining etchant to obtain a CMOS-MEMS chip, and tested. COMSOL multiphysics was used for electro-mechanical evaluation of the inertial system, PSPICE for electrical behavior analysis, Keithley instruments for electrical characterization, and Labview for data acquisition for electrical characterization. In this work, it is demonstrated that an embedded FGMOS can be used to correlate drain current either for static or dynamic inertial parameters. The presented work demonstrates the feasibility to change the coupling coefficient of the FGMOS by means of a MEMS structure, like an accelerometer, to convert displacement into an electrical signal, being suitable for integration in more complex systems.

Analysis and measurement of a photo diode used as a control gate in a floating–gate MOS transistor

This paper reports a new operating use regarding the floating–gate MOS transistor (FGMOS). Here it is demonstrated that the typical open circuit voltage (VOC) of a CMOS integrated photo sensor can be coupled to the floating gate of a FGMOS. Several photo sensors structure designs are studied and measured. Results demonstrated that the threshold voltage of the transistor can be modulated optically with a series array of photo sensors to increase the coupled voltage. Therefore, a micro solar cell integrated with a CMOS technology can be used as a control gate giving an optical alternative to modulate the I–V characteristics of a FGMOS, extending the reliability of this device beyond the known injection phenomena commonly used to program it. Also, more than one control gate can be used with only one transistor, giving opportunity to explore the convenience to use this proposal within a pixel design since only one transistor is used, with its floating gate as a summing node.

Low-Voltage Diode-Less Rectifier Based on Fully Differential Difference Transconductance Amplifier

This paper presents a voltage-mode low-voltage low-power diode-less rectifier with only one active element, the fully differential difference transconductance amplifier (FDDTA). The multiple-input floating-gate MOS (FG-MOS) transistor is used to build the differential pairs of the FDDTA resulting in the reduced count of transistors, circuit simplicity and the capability to work under low-voltage supply with extended input voltage range. The rectifier was designed with 0.9[Formula: see text]V voltage supply and 8[Formula: see text][Formula: see text]W power consumption, hence it is suitable for wearable electronics and biomedical applications. The simulation results obtained from the Cadence platform using 0.18[Formula: see text][Formula: see text]m TSMC CMOS technology show good performances for the designed circuit.

Non-Faradaic Electrochemical Detection of Exocytosis from Mast and Chromaffin Cells Using Floating-Gate MOS Transistors.

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transistor channel from the electrolyte for stable long-term recordings. We measured exocytosis from RBL-2H3 mast cells sensitized by IgE (bound to high-affinity surface receptors FcεRI) and stimulated using the antigen DNP-BSA. Quasi-static I-V measurements reflected a slow shift in surface potential () which was dependent on extracellular calcium ([Ca]o) and buffer strength, which suggests sensitivity to protons released during exocytosis. Fluorescent imaging of dextran-labeled vesicle release showed evidence of a similar time course, while un-sensitized cells showed no response to stimulation. Transient recordings revealed fluctuations with a rapid rise and slow decay. Chromaffin cells stimulated with high KCl showed both slow shifts and extracellular action potentials exhibiting biphasic and inverted capacitive waveforms, indicative of varying ion-channel distributions across the cell-transistor junction. Our approach presents a facile method to simultaneously monitor exocytosis and ion channel activity with high temporal sensitivity without the need for redox chemistry.