Abstract
Sequential logic is essential in many applications as data processing for speech recognition in cochlear implants. In this paper, a family of latches based on floating-gate MOS (FGMOS) transistors is presented. This family takes advantage on the fact that FGMOS logics process data using mostly passive devices, achieving small area and low-power, requirements of modern electronics. Post-layout SPICE simulations from an ON-Semiconductors 0.5 µm CMOS process technology shows improvements over conventional CMOS logic families, making FGMOS latches ideal for low-power applications.
Highlights
Sequential logic is essential in many applications as data processing for speech recognition in cochlear implants
Among these, floating-gate MOS (FGMOS) transistors have demonstrated to achieve power reductions while still maintaining speed in many high performance applications (Aunet, Berg, Tjore, Næss and Sæther 2001).This is possible due to the fact that FGMOS transistors process data within the capacitive network coupled to their gate (Shibata and Ohmi 1992)
As all data processing is carried by the capacitive network of the input FGMOS transistors, Positive Feedback Floating-Gate Logic (PFFGL) achieve minimal transistor count resulting in low- voltage; reduced operational voltage and minimal switching transistors are the most straight-forward way to reduce power
Summary
An architecture that takes advantage of the FGMOS transistors is Positive Feedback Floating-Gate Logic (PFFGL). This logic uses a positive-feedback loop to improve gain in order to reduce errors due to process variability or noise. This way, using smart layout techniques, noise is diminished by the common-mode rejection characteristics of the logic. In order to memorize data, PFFGL sequential gates take advantage of the p-MOS semiconductor It consists of a -channel MOS transistor with a floating gate (first polysilicon layer) over the channel and in some cases extending over to the field oxide area. An array of control gates (multiple input gates) are formed by the second polysilicon layer
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