The p–n junction leakage ( I R) at reverse voltage, which sets the leakage and power consumption of state of the art integrated circuits (ICs) and the DRAM retention time, is mostly related to the peripheral leakage ( I R,p), which is poorly controlled by the defect engineering techniques, opposite to the planar regions. These ICs from their processing till applications cope with irradiation damages, which are side effects of the ICs manufacturing, due to the plasma, e-beam, X-ray and implantation processing, etc. On the other hand, ICs may be submitted to a significant natural radiation level, as e.g. in applications for space satellites and airplane equipment. Therefore, a proper analysis of the I R,p degradation by high-energy irradiation in silicon technology is proposed. It is found that I R,p increases slower for low fluences of neutron irradiation as compared to the leakage of the p–n junction planar regions, so that the I R,p contribution to the total I R decreases. However I R,p still dominates in irradiated small-size junctions. Moreover, for higher fluences the I R,p again strongly increases its contribution to the overall leakage. Deep insight into the underlying physics is obtained by an analysis of the gated diodes current. This method saves test-chip area and testing-time and omits the assumption of the same parasitic leakage for all junctions. Results are reported for n +p gated diodes and p–n junctions in Czochralski, epitaxial and float zone silicon, exposed to 1 MeV fast neutrons with fluences in the range 5×10 11–5×10 13 n/ cm 2 .
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