Flip Chip Package Research Articles

A 65-nm CMOS <inline-formula> <tex-math notation="LaTeX">$2\times2$ </tex-math> </inline-formula> MIMO Multi-Band LTE RF Transceiver for Small Cell Base Stations

This paper presents a 680 MHz–6 GHz $2 \times 2$ multiple-input and multiple-output (MIMO) long-term evolution (LTE) RF transceiver in 65-nm CMOS for low-cost and multi-band capable femtocell base stations. The transceiver integrates two receivers (RXs), two transmitters (TXs), and two frequency synthesizers, for the $2 \times 2$ MIMO operation to support both the frequency division duplex (FDD) and the time division duplex (TDD) modes. Each pair of an RX and a TX features eight single-ended low noise amplifiers (LNAs), and eight TX outputs that extensively share active and passive circuits with minimal performance degradation. In the measurement, each RX illustrates the noise figure (NF) from 2.9 to 5.2 dB, the input-referred third-order intercept point (IIP3) of more than −2 dBm, and the IIP2 of more than 48 dBm, over the entire frequency range at the maximum gain. Each TX achieved the adjacent channel leakage ratio (ACLR) that was less than −54 dBc at −5-dBm output power with −157-dBc/Hz phase noise at the RX band, while achieving an error-vector-magnitude (EVM) of less than 2.8%, over the entire frequency range. The transceiver, packaged in a flip-chip chip-scale package (fcCSP), is mounted on the board of the commercial femtocell of the LTE Band5, along with a commercial duplexer, power amplifier, and modem. The femtocell achieved −100-dBm reference sensitivity without the use of an external LNA. It also achieved −51-dBc TX ACLR and 1.68% TX EVM at 20-dBm output power in the LTE 10-MHz mode with the $2 \times 2$ MIMO configuration, without applying a digital pre-distortion (DPD) technique.

Nondestructive Analysis of Buried Interfacial Behaviors of Flux Residue and Their Impact on Interfacial Mechanical Property

Flux materials are ubiquitously utilized in the microelectronics industry during back-end processing. The Cu oxides or organic solderability preservatives present on Cu posts used in flip-chip packages must be removed by flux before solder reflow and die attachment to ensure a quality connection between the substrate and the die. However, flux residues can cause solder bridging, which renders the device useless. These residues must be studied in situ at the buried interface to determine fundamental interactions and how the residues can be eliminated. In this paper, model flux residues were investigated at the surface and the buried epoxy interface with sum frequency generation vibrational spectroscopy. Glutaric acid. served as the model flux, simulating fluxes that use dicarboxylic acids as one of the main components of the fluxing agent. It was found that the flux residues greatly change the buried interface on both Cu and silica surfaces, which affects properties such as adhesion. It was also observed that the fluxes require long washing times before they are completely removed. This paper is a step forward in flux residue analysis and will help the industry better understand molecular-level details of commonly used processes.

Empirical Equations for Optimization Conditions in Thermal Compression Bonding of Copper Pillar Flip Chip Packages

In this paper, finite element simulations are used to analyze the plastic deformation of the solder ball and its stress and strain distributions. The bonding forces that depend on the forming temperature are investigated. The contact areas between the solder ball and the copper trace are also discussed. The largest contact area is regarded as the optimization condition during the thermal compression bonding processes. The effects of different pillar-trace shift ratios on the contact areas are also discussed to provide a guideline for avoiding product failure. Finally, an empirical equation adopting a four-parameter logistic nonlinear regression model for the pillar-trace gap in terms of the forming temperature and bonding forces is established.

A Low-Cost Scalable 32-Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a <inline-formula> <tex-math notation="LaTeX">$2\times 2$ </tex-math> </inline-formula> Beamformer Flip-Chip Unit Cell

This paper presents a scalable 28-GHz phased-array architecture suitable for fifth-generation (5G) communication links based on four-channel ( $2\times 2$ ) transmit/receive (TRX) quad-core chips in SiGe BiCMOS with flip-chip packaging. Each channel of the quad-core beamformer chip has 4.6-dB noise figure (NF) in the receive (RX) mode and 10.5-dBm output 1-dB compression point (OP1dB) in the transmit (TX) mode with 6-bit phase control and 14-dB gain control. The phase change with gain control is only ±3°, allowing orthogonality between the variable gain amplifier and the phase shifter. The chip has high RX linearity (IP1dB = −22 dBm/channel) and consumes 130 mW in the RX mode and 200 mW in the TX mode at P1dB per channel. Advantages of the scalable all-RF beamforming architecture and circuit design techniques are discussed in detail. 4- and 32-element phased-arrays are demonstrated with detailed data link measurements using a single or eight of the four-channel TRX core chips on a low-cost printed circuit board with microstrip antennas. The 32-element array achieves an effective isotropic radiated power (EIRP) of 43 dBm at P1dB, a 45-dBm saturated EIRP, and a record-level system NF of 5.2 dB when the beamformer loss and transceiver NF are taken into account and can scan to ±50° in azimuth and ±25° in elevation with < −12-dB sidelobes and without any phase or amplitude calibration. A wireless link is demonstrated using two 32-element phased-arrays with a state-of-the-art data rate of 1.0–1.6 Gb/s in a single beam using 16-QAM waveforms over all scan angles at a link distance of 300 m.

Co-optimized Reliability and Parasitic inductance in Small Footprint Vertical Silicon Carbide MOSFET

Abstract Increasing power density in power electronics is driving a need for improved packaging methods for co-optimized high frequency performance, thermal dissipation and reliable operation, especially at high temperatures. Silicon Carbide (SiC) devices offer great opportunity as wide bandgap semiconductor devices, which maintain stability over wide temperature ranges, especially when compared to Silicon (Si) based devices. A novel flip-chip packaging technique for SiC power devices was developed at the University of Arkansas. This new package re-orients a bare die from a lateral device to a vertical device by utilizing a copper connector that routes the drain connection to the top side of the die. This study involves an investigation of achieving a co-optimized packaging configuration for thermomechanical reliability and low parasitic inductance. By orienting this SiC switch vertically, the unique 3D drain connector dramatically reduces the ringing at aggressive switching speeds used in power electronics when compared to Commercial Off The Shelf (COTS) devices. However, the design of this drain connector holds importance for high temperature operation, interconnect reliability as well as manufacturability. Effects of the packaging design, including materials, layout and solder pitch size were investigated from a thermal cycling reliability aspect. Electrical performance, such as parasitic inductances of the device, was also investigated using Finite Element Analysis (FEA) simulation. Several drain connector architectures were evaluated for their fatigue life capability of solder interconnects under thermal cycling (according to Darveaux's model) in conjunction with the parasitic inductance using FEA simulation. Based on the simulation results, an optimized architecture was selected and fabricated for prototype demonstration, and the electrical performance under double pulse test compared with state of the art devices demonstrated improvement in switching performance by reducing overshoot of voltage across the grain-source by 36% and 77% reduction of the drain current ringing during the turn-off event while eliminating voltage overshoot during turn-on event for the testing conditions.

(Invited) Indium Gallium Phosphide Photodiode with 50% Increased External Quantum Efficiency and Higher Signal to Noise Ratio for Blood Pressure Measurement

Measurement of blood pressure is one of the most important parameters for personal healthcare. Arteries are responsible for carrying blood from the heart to all parts of the body and the pressure of blood in arteries is measured in many abnormalities. The blood pressure is explained by two parameters. The highest blood pressure during heart pumping is measured by systolic pressure whereas the diastolic pressure measures the lowest blood pressure when the heart is not pumping the blood. For current work, the principle of light absorption is used to measure blood pressure in arteries. Light is more strongly absorbed by blood compared to skin or tissues and therefore, blood flow change can be detected by the change in intensity of light. This blood flow change is proportional to blood pressure and hence the blood pressure can be measured by measurement of change in light intensity. In this work, we have developed the InGaP photodiode module with higher signal to noise ratio for blood pressure measurement. The InGaP photodiode External Quantum Efficiency (EQE) is 50% higher than Silicon (Si) photodiode. The EQE is ever higher than Si photodiode equipped with the filter as shown in Fig. 1(a). The newly developed InGaP photodiode has the advantage of selective EQE at different wavelength. The photodiode has almost zero EQE outside the desired region of wavelength (300 nm- 700 nm) where the Si photodiode EQE is spread in the longer wavelength region (300 nm - 1200 m). This higher region of EQE can lower the signal to noise ratio. The InGaP photodiode has an increased signal to noise ratio (24.8) compared to other photodiodes (24.0) due to the smaller wavelength region of EQE. Both systolic blood pressure and diastolic blood pressure measurement was compared for actual value and predicted value. The R2 correlation value for systolic and diastolic blood pressure is measured to be 0.86 and 0.91 respectively as shown in Fig. 1(b) and Fig. 1(c). This works explore new doorway for LED and photodiode application in the field of biomedical sensors. The application of our new photodiode with enhanced EQE and the wide range of LED has numerous possibilities. The higher possibility of multichip design with Flip chip packaging technique can provide a single module for measurement of blood pressure, blood glucose, blood lipid and other parameters using LED of different wavelength. Figure 1

Packaging of InGaN stripe-shaped light-emitting diodes.

We demonstrate the fabrication of InGaN/GaN stripe-shaped light-emitting diodes (LEDs) in flip-chip packaging (FC-LED) and vertically mounted packaging (VM-LED). Compared to conventionally packaged LEDs, these packaging schemes enhance light output and emission divergence in ways favorable for general lighting applications. The FC-LED can sustain efficiency at high current operations due to effective heat sinking, while the VM-LED excels at light extraction efficiency due to the exposure of two large emission surfaces. Together with the properties of low luminous exitance and emission uniformity, the stripe-shaped LEDs are ideal for the assembly of luminaires. An LED light tube comprising a continuous linear array of 10 stripe-shaped LED chips has been assembled. The optical performance of the light tube is compared to another light tube assembled with conventional square-shaped LED chips (with and without external diffuser) by confocal microscopy. It is found that emission uniformity of the stripe-shaped LED tube is significantly improved, with a threefold increase in illumination area, without efficiency loss associated with diffusers.

A Further Study on the Analytical Model for the Permeability in Flip-Chip Packaging

The notion of permeability is very important in understanding and modeling the flow behavior of fluids in a special type of porous medium (i.e., the underfill flow in flip-chip packaging). This paper presents a new concept regarding permeability in a porous medium, namely two types of permeability: superficial permeability (with consideration of both the pore cross-sectional area and the solid matrix cross-sectional area) and pore permeability (with consideration of the pore cross-sectional area only). Subsequently, the paper proposes an analytical model (i.e., equation) for the pore permeability and superficial permeability of an underfill porous medium in a flip-chip packaging, respectively. The proposed model along with several similar models in literature is compared with a reliable numerical model developed with the computational fluid dynamics (CFD) technique, and the result of the comparison shows that the proposed model for permeability is the most accurate one among all the analytical models in literature. The main contributions of the paper are as follows: (1) the provision of a more accurate analytical model for the permeability of an underfill porous medium in flip-chip packaging, (2) the finding of two types of permeability depending on how the cross-sectional area is taken, and (3) the correction of an error in the others' model in literature.

Fundamental Problems of Flip-chip Package and Low Temperature Assembly

Fundamental Problems of Flip-chip Package and Low Temperature Assembly

RGB-Stack Light Emitting Diode Modules with Transparent Glass Circuit Board and Oil Encapsulation

The light emitting diode (LED) is widely used in modern solid-state lighting applications, and its output efficiency is closely related to the submounts’ material properties. Most submounts used today, such as low-power printed circuit boards (PCBs) or high-power metal core printed circuit boards (MCPCBs), are not transparent and seriously decrease the output light extraction. To meet the requirements of high light output and better color mixing, a three-dimensional (3-D) stacked flip-chip (FC) LED module is proposed and demonstrated. To realize light penetration and mixing, the mentioned 3-D vertically stacking RGB LEDs use transparent glass as FC package submounts called glass circuit boards (GCB). Light emitted from each GCB stacked LEDs passes through each other and thus exhibits good output efficiency and homogeneous light-mixing characteristics. In this work, the parasitic problem of heat accumulation, which caused by the poor thermal conductivity of GCB and leads to a serious decrease in output efficiency, is solved by a proposed transparent cooling oil encapsulation (OCP) method.

Laser printing of flip-chip interconnects for high frequency applications

We demonstrate flip-chip interconnects using laser-induced forward transfer (LIFT) of Ag nanopaste. To achieve this, Ag nanopaste interconnects were laser printed directly onto the bond pads of an RF switch. The devices were bonded to test fixtures via reflow processing, eliminating the need for thermocompression bonding. High frequency measurements were performed on both a switch with laser printed / reflow cured interconnects and a wire-bonded switch. After bonding, the RF switch with laser printed interconnects performed similar to a wirebonded switch, confirming the bonding process does not degrade high frequency performance. This result implies that laser printing directly onto device bond pads in combination with reflow processing offers a fast and efficient alternative to current flip-chip packaging techniques.

Defect inspection of flip chip package using SAM technology and fuzzy C-means algorithm

Solder bumps are widely used in surface mount components, which provide electrical and mechanical connection between the chip/package and the substrate. As the solder bump getting smaller in dimension and pitch, it becomes more difficult to inspect the solder defects hidden in the IC package. In this paper, an intelligent inspection method using the scanning acoustic microscopy (SAM) and the fuzzy C-means (FCM) algorithm was investigated. A flip chip package of FA10 was chosen as the test sample. The SAM tests of FA10 were carried out in C-scan mode. The sub-image of every solder bump was segmented from the SAM image. The statistical features were then calculated and adopted for clustering of solder bumps using the FCM algorithm. The recognition results of FCM reached a high accuracy of 94.3%. The intelligent system is effective for defect inspection in high density packages.

High-Efficiency Revolving-Turret Chip Transferring Technology for Flip Chip Packaging

With the rapid growth of the microelectronic packaging market, it is necessary to increase the throughput and reduce the cost of flip chip. Driven by these evolutions, a novel revolving-turret chip transferring (RTCT) technology is introduced to implement high-throughput flip chip packaging. The unnecessary time delays of packaging processes could be eliminated in the RTCT technology due to its parallel manner of motions. In order to analyze the packaging efficiency, the layout and movement sequence of the packaging system are studied, and a calculation model of packaging efficiency is proposed. Furthermore, the effects of the critical parameters (the horizontal and the vertical spacing of antennas and the maximum velocity and acceleration of the turret-type head) on packaging efficiency are investigated to search out the optimal parameters combination. To verify the performance of the RTCT technology under optimal parameters combination, two cases are implemented and compared. The results show that due to parallel motions of processes, unnecessary delays affecting the packaging efficiency have been reduced, and the packaging efficiency of ALN-9714 inlay could be more than 35k chips per hour. In addition, compared with the conventional flip chip packaging process, the RTCT technology is more effective in packaging the chips on antennas with multicolumn layout and small horizontal spacing.

Configuration for High-speed Transmission between Flip-chip Packages Using Low Loss and Flexible Substrate

Configuration for High-speed Transmission between Flip-chip Packages Using Low Loss and Flexible Substrate

反射式倒装对1 300 nm激光器性能改善的分析

反射式倒装对1 300 nm激光器性能改善的分析

Interfacial reaction and failure mechanism of Cu/Ni/SnAg1.8/Cu flip chip Cu pillar bump under thermoelectric stresses

Micro-interconnection copper pillar bumps are being widely used in the packaging areas of memory chip and high performance computer due to their high density, good conductivity and low noise. Studying the interfacial behavior of copper pillar bump is of great significance for understanding its failure mechanism and microstructure evolution in order to improve the reliability of flip chip package. The thermoelectric stress test, in-situ monitor, infrared thermography test, and microstructure analysis method are employed to study the interfacial reaction, life distribution, failure mechanism and their effect factors of Cu/Ni/SnAg1.8/Cu flip chip copper pillar interconnects under 9 groups of thermoelectric stresses including 2104-3104 A/cm2 and 100-150℃. Under thermoelectric stresses, the interfacial reaction of Cu pillar can be divided into three stages:Cu6Sn5 growth and Sn solder exhaustion; the Cu6Sn5 phase transformation, exhaustion and the Cu3Sn phase growth; voids formation and crack propagation. The rate of Cu6Sn5 phase transforming into Cu3Sn phase is positively correlated with the current density. There are four kinds of failure modes including Cu pad consumption, solder complete consumption and transformation into Cu3Sn, Ni plating layer erosion and strip voids. An obvious polar effect is observed during the dissolution of Cu pads on the substrate side and the Ni layer on the Cu pillar side. When Cu pad is located at the cathode, the direction of electron flow is the same as that of the heat flow, and it can accelerate the consumption of Cu pad and the growth of Cu3Sn. When Ni layer serves as the cathode, the electron flow can enhance the consumption of Ni layer. Under 150℃ and 2.5104 A/cm2, the local Ni barrier layer is eroded after 2.5 h, which results in the transformation of Cu pillar on the Ni side into (Cux, Niy)6Sn5 and Cu3Sn alloy. The life of Cu pillar interconnection complies well to the 2-parameter Weibull distribution with a shape parameter of 7.78, which is a typical characteristic of cumulative wear-out failure. The results show that the intermitallic growth behavior and failure mechanism at Cu pillar interconnects are significantly accelerated and changed under thermoelectric stresses compared with the scenario under the single high temperature stress.

Analytical thermal stress model for a typical flip-chip (FC) package design

A simple analytical thermal stress model is suggested for a typical flip-chip (FC) lidded package design. The model is based on the concept of the interfacial compliance. The addressed design consists of a silicon FC bonded to an organic substrate and covered by a lid. The lid is configured in such a way that its mid-portion is bonded to the back side of the chip using a thermal interface material (a heat sink is intended to be subsequently mounted on the outer surface of the lid) and the lid’s peripheral portions are adhesively bonded to the same substrate using compliant attachments around the lid’s perimeter. A copper lid and a (hypothetical) organic lid are considered to develop a general feeling of the possible stress relief that could be expected if an organic lid is employed. The in-plane compliances of all the attachments, including the effective compliance of the encapsulated solder joint interconnections, are taken into account. A numerical example shows how the model could be used in practical computations. It shows also that the application of an organic lid, although is less attractive from the standpoint of the thermal management of the design, might result in appreciably lower thermal stresses. This is true for both the normal stresses in the chip’s cross-sections and the maximum interfacial shearing stresses at the chip’s ends. The developed model can be employed in the analysis of a FC package design of the type in question. Future work should include FEA verifications, and the suggested analytical stress model can be of help when developing a FEA preprocessing simulation model.

Fabrication and Characterization of a GaN-Based 320 × 256 Micro-LED Array**Supported by the National Key Research and Development Program under Grant No 2016YFB0400902, and the Science and Technology Project of State Grid Corporation of China under Grant No SGSDDK00KJJS1600071.

Design, fabrication and characterizations of GaN-based blue micro light emitting diode (LED) arrays are reported. The GaN micro-LED array consists of 320 × 256 pixels with a pitch size of 30μm. Each pixel is 25 × 25 μm2 in size, which is designed for backside emission and high density flip-chip packaging. The selected LED pixels being tested exhibit good uniformity in terms of turn-on voltage and reverse leakage current. The efficiency droop behavior and reliability behavior under high forward current stress are also studied. The micro-LED pixel shows improved reliability, which is likely caused by enhanced heat dissipation.

Analyses and statistics of the electrical fail for flip chip packaging by using ANSYS simulation software and really underfill materials

ANSYS simulation software has gold standard for modeling and simulating surface chemistry reactions that are used for the conceptual development of combustion systems in chemical and materials processing equipment. In this study, three different models of the solder bumps were arranged, designed, and simulated by ANSYS simulation software. The first model was a single solder bump, which had the height of 70 µm and diameter of 115 µm, and the both diameters to contact upper chip and lower substrates were 90 µm. The second model was that the single solder bumps were arranged to form an array with different spacing between two “single solder bumps”, the area and height were 1520 μm × 3610 μm and 70 μm. The third model was that the single solder bumps with two different arranged arrays were formed on the substrates on different sides, the distances between two “single solder bumps” had different values in the two arranged arrays, and the area and height for this model were 2600 μm × 2570 μm and 70 μm. We would use five differently underfill materials with different properties (including viscosity) as the simulated parameters in the third model. Finally, the five underfill materials were used in the dispensing experiment to find the optimum one for the flip chip packaging.

Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology

Abstract Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effectiveness. The increasing complexities in achieving a higher degree of performance, bandwidth and better power efficiency in various markets are pushing the boundaries of emerging packaging technologies to smaller form factor packaging designs with finer line/width spacing as well as improved thermal/electrical performance and the integration of System-in-Package (SiP) or 3D capabilities. SiP technology has been evolving through utilization of various package technology building blocks to serve the market needs with respect to miniaturization, higher integration, and smaller form factor as cited above, with the added benefits of lower cost and faster time to market as compared to silicon (Si) level integration, which is commonly called system-on-chip or SoC. As such, SiP incorporates flip chip (FC), wire bond (WB), and fan-out wafer-level packaging (FOWLP) as its technology building blocks and serves various end applications ranging from radio frequency (RF), power amplifiers (PA), Micro-Electro-Mechanical-Systems (MEMS) and Sensors, and connectivity, to more advanced application processors (AP), and other logic devices such as graphics processing units (GPUs)/central processing units (CPUs). FOWLP, also referred to as advanced embedded Wafer Level Ball Grid Array (eWLB) technology, provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D SiP configurations. This paper presents developments in SiP applications with eWLB/Fan-out WLP technology, integration of various functional blocks such as wire bonding, Package-on-Package (PoP), 2.5D, 3D, smaller form factor, embedded passives, multiple redistribution layer routing and z-height reduction. Test vehicles have been designed and fabricated to demonstrate and characterize these low profile and integrated packaging solutions for mobile products including Internet of Things (IoT)/wearable electronics (WE), MEMS and sensors. Finer line/width spacing of 2/2mm with multiple redistribution layers (RDL) are fabricated and implemented on the eWLB platform to enable higher interconnect density and signal routing. Assembly process details, component level reliability, board level reliability and characterization results for eWLB SiP will be discussed.