Flip Chip Package Research Articles

FOWLP and Flip Chip Cost Comparison: Impact of the Supply Chain Crunch

The impact of the pandemic on the semiconductor and electronics packaging supply chains has been in the news for over a year now. Current projections suggest the supply chain crunch could impact various industries through 2022 and 2023. While there are many ramifications of this shortage, one is certainly the impact on cost. Pricing for packages built with more mature technologies, such as wire bond and flip chip, has changed dramatically. Both of these mature technologies have typically been seen as lower cost options than newer technologies, such as fan-out wafer level packaging (FOWLP). Due to the recent shortages, the cost comparison is no longer as straight-forward as it was before. This paper will analyze the cost of building various packages using flip chip, wire bond, and FOWLP technologies. Factory overhead, indirect costs, and profit margins will be taken into account to turn this into a price comparison, rather than just a comparison of direct costs. The analyses will include the price of a package built using FOWLP technology, the price of flip chip and wire bond packages built before recent supply chain disruptions, and the new expected prices of flip chip and wire bond packages. Activity based cost modeling will be used for this analysis. This is a bottom-up, detailed approach to cost that accounts for the many cost components associated with every step of the process flow, such as material, labor, and capital depreciation. The goal of this analysis is to understand how supply chain disruptions have changed the cost parity points of wire bond, flip chip, and FOWLP packages.

Thermal contact analysis of Flip-Chip package considering microscopic contacts of double-layer thermal interface materials

Flip-chip packaging technology is widely used in the field of electronic packaging. The thermal contact resistances (TCRs) of its double-layer thermal interface materials (TIMs) impact its thermal characteristics. In this paper, a flip-chip package thermal contact model is first constructed considering the internal rough contact interface of double-layer TIMs. Secondly, the effects of friction coefficient, pressure, elastic modulus of double-layer TIMs, thermal conductivity of double-layer TIMs, interstitial medium, and convective heat transfer coefficient on the flip chip package's contact mechanics and thermal properties are analyzed. Finally, the influence of secondary thermal effects on contact mechanics and thermal properties is investigated. The results show that the friction coefficient, pressure, and elastic modulus of double-layer TIMs have a significant influence on the TCRs by changing the actual contact area, but the impact on the heat dissipation of the chip is limited, and the maximum temperature reduction does not exceed 10 K. However, the interstitial medium, convective heat transfer coefficient, and thermal conductivity of double-layer TIMs greatly influence the heat dissipation of the chip and maximum temperature by directly affecting heat transfer performance. Furthermore, secondary thermal effects have varying degrees of influence on contact stiffness, TCRs, and temperature distribution.

CU Wirebond Technology in 16FFC High Performance Automotive Radar Processor with IR Drop Reduction Methodology

High performance automotive radar front-end processors normally use advanced semiconductor packaging such as Flip Chip, fan-in and fan-out wafer level Ball Grid Array (BGA) packages in order to provide superior performance in their applications. However, for a cost effective package in the competitive business market, wirebonded package can also provide similar uncompromised performance. Advanced Cu wirebond technology was evaluated on the 16FFc radar processor. However, the challenge of high voltage drop, also known as IR drop, in 16FFc technology has to be overcome. As wafer technology moves to smaller advanced nodes, the back-end-of-line (BEOL) metal thickness gets thinner, thus increasing the resistance per unit length. Another trend in semiconductor design has been a reduction in operating voltage, meaning that small changes in supply voltage may represent an increasing percentage of the digital swing and potentially lead to incorrect logic values. As current flows through a resistor, the high voltage drop could slow down the circuitry, impact the circuit timing and lead to functional failure. In order to reduce the IR drop in the radar processor when using Cu wirebond, a large quantity of intra-die wires was applied on the 16FFc silicon. IR drop simulation was performed on 3 layout conditions, 0%, 50% and 100% of the intra-die wires. Empirical data was also collected with actual Cu wirebonded samples. The fully populated intra-die wires reduced IR drop by 30%. To enable the reliable performance of the intra-die wires, Stand-off Stitch Bond (SSB) wirebond technology was introduced within the package. The development and reliability evaluation was conducted for Cu wirebonding on 16FFc automotive radar processor of 30mm2 die size in a 14mm x14mm 2-layer substrate BGA package. Wirebond recipe was developed based on detailed Design of Experiment to establish bonding parameters for both standard wires and the intra-die wires. Packages were tested per AEC Grade 1 and AEC Q006 qualifications requirements. All results from package reliability assessments passed with no abnormality. Board level temperature cycling reliability for the BGA package with the four depopulated corner solder balls was evaluated with results surpassing NXP requirement for AEC Grade 1. This paper will present the results and analysis from (1) IR drop simulation and empirical data collection, (2) wirebond development and reliability of standard and intra-die wires on 16FFc Silicon, and (3) board level reliability of a BGA package with four depopulated corner solder balls.

Validating Flip Chip Package Models Through Experimental Deflection Measurements

Tektronix Component Solutions is advancing its simulation capabilities to improve product reliability, reduce development costs, and speed up time-to-market. Developing a model that accurately predicts performance requires that it be validated through correlation to real-world results. In this work, a high-fidelity, multi-step, nonlinear finite element model was built including processing steps and thermal cycling to mirror the real environment of a flip chip package. Extensive materials characterization was performed to capture accurate time-and-temperature dependent (viscoelastic) properties of the underfill adhesive, stiffener ring adhesive, and substrate components. Model accuracy was established through three measurement techniques to characterize package deflections. The Thermo-Moiré technique was used to measure package warpages as a function of processing step and thermal loading. Optical Interferometry was used as a secondary approach to measure package warpage as a function of processing step. Lastly, Digital Image Correlation was performed on a cross-section of the package to characterize shear and through-thickness strains of critical solder bumps. The simulation produced excellent correlation with the various measurement techniques, and it was found that component pre-warpage (inherent to the substrate and stiffener ring) was a necessary variable to account for during simulation and measurement. With the excellent correlation provided by the models, Tektronix Component Solutions is now using these methods in combination with material strength testing to advance critical stress and survivability predictions in advanced packages.

Cost Analysis of Fan-out Processes for Chiplet Packaging

When building a design around chiplets, there are many factors to consider: industry standards, availability of chiplets within the supply chain, size requirements, and cost, to name a few. The cost of chiplet packaging is a particularly important factor that must be understood, because even if all design requirements can be met, the chiplet package will not come to fruition if the total cost is too high. The basic tradeoff between a monolithic die and a series of chiplets is a reduction in silicon costs countered by an increase in packaging costs. This analysis will compare a monolithic die flip chip package to two fan-out processes that support chiplet packaging. In the first scenario, a two-chiplet chip-last fan-out on substrate package will be compared to a standard flip chip package. For the second comparison, a monolithic flip chip package will be compared to a four-chiplet fan-out package that utilizes embedded silicon for additional interconnect. For both scenarios, a detailed cost comparison will be provided. Activity based cost modeling will be used for this analysis. In addition to looking at the direct costs of the substrate and assembly processes, yield considerations and the price of the incoming silicon (which varies by node) will be included. The goal of this analysis is to evaluate the cost of a monolithic flip chip package versus a chiplet scenario for two designs, and to highlight the cost drivers of the fan-out chiplet packaging processes.

Comparative study of solder joint reliability assessment on fan-out CSP and flip-chip DCA package

Comparative study of solder joint reliability assessment on fan-out CSP and flip-chip DCA package

Experimental and numerical study of solder bumps impact on the underfill fluid flow under electrohydrodynamic effect

Solder bumps can increase filling time, which is one of the main challenges in electronic packaging reliability. Here, we compare the capillary flow behavior between parallel plates with and without solder bumps to examine how solder bumps affect the length of the underfill fluid flow under the effects of an electric potential. We found that the solder bumps restrained the flow length, while the electric field enhanced it. By enhancing the voltage from 0 to 1000 V, in the case without solder bumps, the flow length increased by up to 30%, and it increased by up to 25% in the case of solder bumps. To determine the optimum bump design, we selected the diameter and pitch size of the solder bumps as the independent variables. The results revealed that larger pitch sizes and smaller diameters show longer fluid flow lengths. The effect of the electric field on varying nozzle positions was also investigated. We found that the fluid flow length increased when the nozzle was between the solder bumps compared to the top of the solder bumps. According to our observations, the nozzle position is also the main factor in determining the fluid flow length compared with the bump diameter and pitch sizes for the design of the underfill packaging process. Numerical simulations were also performed to compare the experimental results, and the average discrepancy between the experimental and numerical results at various time steps for different solder bump parameters was between 5 to 10%. Our findings demonstrate the potential of using electric potential in conjunction with solder bumps to control underfill flow, which can benefit flip-chip packaging applications. Numerical methods can accurately predict underfill fluid flow with solder bumps under the electric field effect.

Development of ANN-Based Warpage Prediction Model for FCCSP via Subdomain Sampling and Taguchi Hyperparameter Optimization.

This study aims to establish an accurate prediction model using artificial neural networks (ANNs) to effectively and efficiently predict the process-induced warpage of a flip-chip chip-scale package (FCCSP). To enhance model performance, a novel subdomain-based sampling strategy and Taguchi hyperparameter optimization are proposed in the ANN algorithm. To simulate the warpage behavior the FCCSP during fabrication, a process modeling approach is proposed, where the viscoelastic behavior of the epoxy molding compound is included, in which the viscoelastic properties are determined using dynamic mechanical measurement. In addition, the temperature-dependent thermal-mechanical properties of the materials in the FCCSP are assessed through thermal-mechanical analysis and dynamic mechanical analysis. The modeled warpage results are verified by the warpage measurement. Next, warpage parametric analysis is performed to identify the key factors most affecting warpage behavior for use in the construction of the warpage prediction model. Moreover, the advantages of the proposed sampling and hyperparameter tuning approaches are proved by comparing with other existing models, and the validity of the developed ANN-based deep learning warpage prediction model is demonstrated through a validation dataset.

Reliability Analysis of Flip-Chip Packaging GaN Chip with Nano-Silver Solder BUMP.

Gallium nitride (GaN) power devices have many benefits, including high power density, small footprint, high operating voltage, and excellent power gain capability. However, in contrast to silicon carbide (SiC), its performance and reliability can be negatively impacted by its low thermal conductivity, which can cause overheating. Hence, it is necessary to provide a reliable and workable thermal management model. In this paper, a model of a flip-chip packing (FCP) GaN chip was established, and it was assigned to the Ag sinter paste structure. The different solder bumps and under bump metallurgy (UBM) were considered. The results indicated that the FCP GaN chip with underfill was a promising method because it not only reduced the size of the package model but also reduced thermal stress. When the chip was in operation, the thermal stress was about 79 MPa, only 38.77% of the Ag sinter paste structure, lower than any of the GaN chip packaging methods currently in use. Moreover, the thermal condition of the module often has little to do with the material of the UBM. Additionally, nano-silver was found to be the most suitable bump material for FCP GaN chip. Temperature shock experiments were also conducted with different UBM materials when nano-silver was used as bump. It was found that Al as UBM is a more reliable option.

Reliability Evaluation of Board-Level Flip-Chip Package under Coupled Mechanical Compression and Thermal Cycling Test Conditions.

Flip Chip Ball Grid Array (FCBGA) packages, together with many other heterogeneous integration packages, are widely used in high I/O (Input/Output) density and high-performance computing applications. The thermal dissipation efficiency of such packages is often improved through the use of an external heat sink. However, the heat sink increases the solder joint inelastic strain energy density, and thus reduces the board-level thermal cycling test reliability. The present study constructs a three-dimensional (3D) numerical model to investigate the solder joint reliability of a lidless on-board FCBGA package with heat sink effects under thermal cycling testing, in accordance with JEDEC standard test condition G (a thermal range of -40 to 125 °C and a dwell/ramp time of 15/15 min). The validity of the numerical model is confirmed by comparing the predicted warpage of the FCBGA package with the experimental measurements obtained using a shadow moiré system. The effects of the heat sink and loading distance on the solder joint reliability performance are then examined. It is shown that the addition of the heat sink and a longer loading distance increase the solder ball creep strain energy density (CSED) and degrade the package reliability performance accordingly.

Reliability and failure modelling of microelectronic packages based on ultrasonic nondestructive evaluation data

Reliability testing and failure modelling is crucial and very challenging for modern electronics, especially safety critical electronics-based systems working under harsh environmental conditions. In this paper, an approach based on ultrasonic Non-Destructive Evaluation (NDE) is proposed to establish a failure model for solder joints which is urgently needed for prognostic and health management of electronics. Printed Circuit Boards (PCB) containing flip-chip and Area Array packages were designed and aged using Accelerated Thermal Cycling (ATC) testing. During ATC testing solder joint degradation was regularly monitored by taking out the test boards from the temperature chamber at four thermal cycle intervals for ultrasonic micro-imaging. Data pre-processing techniques including dynamic range-based intensity normalization, gain compensation, and calibration for random transducer defocusing errors were developed to enhance the data consistency, integrity and accuracy. Furthermore, solder joint image labelling and segmentation methods were developed by exploiting the geometrical features of the solder joints to extract individual solder joints and Region of Interests (ROIs) from the sequential ultrasound images collected throughout the testing. The mean intensity of the ROIs was used as the precursor to degradation to build the solder joint failure model, from which cycles to failure for individual solder joints are finally derived for life prediction.

Numerical investigation on rheology models during encapsulation of moulded underfill (MUF) for flip-chip package

Numerical investigation on rheology models during encapsulation of moulded underfill (MUF) for flip-chip package

A Physics-of-Failure Investigation of Flip Chip Reliability Based on Lead-Free Solder Fatigue Modeling

Solder fatigue failure is one of the primary wear out failure mechanisms limiting reliability in microelectronics flip chip packaging. Solder fatigue failure occurs when a crack initiates and subsequently propagates through the entirety of the solder joint causing an electrical open. Crack initiation and propagation within a solder joint is caused by a cyclic application of stress, typically induced by exposure to temperature cycle excursions. Understanding the relationship between thermal cycling during product use and the accelerated thermal cycles used for testing is critical for predicting device reliability. MIL-PRF-38535 is the guiding aerospace and high reliability General Specification for Integrated Circuits (Microcircuits) Manufacturing that defines manufacturing, qualification and certification requirements for products to be listed on the Defense Logistic Agency’s (DLA) Qualified Manufacturer Listing (QML). Revision M of this standard, targeted for release in 2022, for the first time includes the use of lead-free solder alloys and organic substrates in the manufacturing of QML flip chip products. Hence there is a strong need to understand the physics-of-failure (PoF) concerning solder fatigue of lead-free flip chip assemblies. This paper demonstrates how finite element modeling can be used to predict solder fatigue for flip chip package assemblies. The authors have leveraged fatigue lives measured for different flip chip daisy chain package configurations, as well as fatigue lives defined and available in published papers. The authors then use the resulting lead-free solder fatigue model to perform parametric studies looking at the impact of different die sizes, underfill material properties, and package substrate materials. Comparisons are also made between eutectic Sn/Pb and lead-free fatigue life predictions. In addition, the authors demonstrate how solder fatigue predictions can be de-rated to use conditions in order to make reliability assessments for flip chip package assemblies. This ultimately leads to a better understanding of the impact of solder alloy and material selection on the mission life of aerospace and high reliability products that fall under the changes introduced in MIL-PRF-38535 Revision M.

Board Level Reliability of Flipchip Package

In the world of electronic materials, solder is a critical material that plays an important role in the first level (silicon to package substrate) and second level (package to printed circuit board) interconnection. As a joining material in electronic assemblies, solder provides electrical and mechanical connections. The increasing need for reliable electronic devices for harsh environment triggers the need for reliable solder joints. This study focuses on reliability of second level interconnections between package and printed circuit boards. Board level temperature cycling and mechanical drop performance of a 15 mm x 15 mm FCBGA test vehicle were evaluated with different package construction (lidded vs non-lidded), and BGA solder alloys (SA1, SA2, and SA3). Daisy chain packages were assembled on 1.0 mm thick PCB. Mounted units were thermally cycled between from -40C to 125C. Additional samples were evaluated in mechanical drop test conditions following JEDEC standards. Results showed that packages with SA2, and SA3 BGA had significantly higher board-level thermal cycling life compared to SA1. The best drop performance was achieved with SA1 solder. The performance trend among different solder alloys was found to be similar between lidded vs non lidded package. However, lidded package showed improved board-level reliability performance compared to a non-lidded package.

Thermal Analysis of Flip-Chip Bonding Designs for GaN Power HEMTs with an On-Chip Heat-Spreading Layer

In this work, we demonstrated the thermal analysis of different flip-chip bonding designs for high power GaN HEMT developed for power electronics applications, such as power converters or photonic driver applications, with large gate periphery and chip size, as well as an Au metal heat-spreading layer deposited on top of a planarized dielectric/passivation layer above the active region. The Au bump patterns can be designed with high flexibility to provide more efficient heat dissipation from the large GaN HEMT chips to an AlN package substrate heat sink with no constraint in the alignment between the HEMT cells and the thermal conduction bumps. Steady-state thermal simulations were conducted to study the channel temperatures of GaN HEMTs with various Au bump patterns at different levels of current and voltage loadings, and the results were compared with the conventional face-up GaN die bonding on an AlN package substrate. The simulations were started from a single finger isolated HEMT cell and then extended to multiple fingers HEMT cells (total gate width > 40 mm) to investigate the "thermal cross-talk" effect from neighboring devices. Thermal analysis of the GaN HEMT under pulse operation was also performed to better reflect the actual conditions in power conversion or pulsed laser driver applications. Our analysis provides a combinational assessment of power GaN HEMT dies under a working condition (e.g., 1MHz, 25% duty cycle) with different flip chip packaging schemes. The analysis indicated that the channel temperature rise (∆T) of a HEMT cell in operation can be reduced by 44~46% by changing from face-up die bonding to a flip-chip bonding scheme with an optimized bump pattern design.

Intelligent diagnosis of flip chip solder joints with resolution enhanced SAM image

Scanning acoustic microscopy (SAM) technique has been applied to defect inspection in electronic devices. With the increase of packaging density, detection of the micro-defects in high density devices becomes more and more challenging. The SAM test is suffering from sacrificing the spatial resolution to reach a certain penetration depth of the ultrasonic waves. So it is necessary to enhance the resolution level of the SAM image. In this paper, a wavelet based resolution enhancement technique was investigated to reconstruct a high quality image for SAM test of the flip chip packages. The stationary wavelet transform was adopted to decompose the captured SAM image into four frequency subbands, and the high frequency subbands were enhanced by adding the difference matrix in the intermediate stage, and a super resolution SAM image was derived from combining all the subbands by using the Inverse Discrete Wavelet Transform. Then the solder joints segmented from the SR-SAM image were classified by using the SVM algorithm. The results validated that the proposed technique is effective to improve the detection accuracy of SAM test.

Low threshold current density and high power InGaN-based blue-violet laser diode with an asymmetric waveguide structure.

Performance of InGaN-based blue-violet laser diodes (LD) with different waveguide structure were investigated by simulation and experimental methods. Theoretical calculation demonstrated that threshold current (Ith) can be reduced and slope efficiency (SE) can be improved by using an asymmetric waveguide structure. Based on the simulation results, a LD with 80-nm-thick In0.03Ga0.97N lower waveguide (LWG) and 80-nm-thick GaN upper waveguide (UWG) is fabricated with flip chip package. Under continuous wave (CW) current injection at room temperature, its optical output power (OOP) reaches 4.5 W at an operating current of 3 A and the lasing wavelength of 403 nm. The threshold current density (Jth) is 0.97 kA/cm2 and the SE is about 1.9 W/A.

An 11.6aF/kPa Mechanical Stress Sensor With 0.808% Temperature-Drift Oscillator for Flip-Chip Packaging

During the package processes, including chip attachment and encapsulation, the stress caused by the thermal and mechanical load is usually generated in integrated circuit chips. This brief developed a mechanical stress sensor in a standard 180nm CMOS process for runtime stress measurement. The contributions done in this brief are summarized as follows: 1) A temperature-compensation RC oscillator circuit converts the warpage of the die induced by the mechanical stress into the frequency output. It even can measure the thermally induced stresses with a wide temperature range. The oscillator has a frequency variation of −0.808% from temperature stability measurements from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 40^{\circ }\text{C}$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$120^{\circ }\text{C}$ </tex-math></inline-formula> . 2) Rather than the complicated calibrations and advanced measurement equipment, the frequency can be easily measured with the chip area less than 0.569 mm2 and the power consumption less than 22.9 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> . 3) As for the sensing array, the sensitivity and stability of the metal-insulator-metal (MIM) and metal–oxide–metal (MOM) capacitors are verified. The measured average sensitivity of the test chip using a MIM capacitor with 0.1736 Hz/kPa is more sensitive than that using a MOM capacitor with 0.102 Hz/kPa. The linear fit curves of the output frequency have the coefficient of determination ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{R}^{2}$ </tex-math></inline-formula> ) of 0.9983 for MIM and 0.9959 for MOM, indicating an excellent linear response of the sensor circuit.

Effects of underfill on wideband flip-chip packaging for 5G millimeter-wave applications

This letter investigates the effects of the underfill on the wideband flip-chip packaging for 5G millimeter-wave (mm-Wave) applications. For accurate interconnect design, a new hybrid equivalent circuit model is proposed. Targeting at the phased array systems with high density I/Os, a compact anti-pad structure is implemented and co-designed with the high impedance transmission line and the low-cost 90 μm solder balls, compensating the flip-chip capacitive parasitics and realizing the compact low-loss interconnect. To evaluate the underfill effect on the interconnect parasitics, both theoretical analyses and simulations are undertaken. For demonstration, by using a glass substrate with the fan-out process, back-to-back flip-chip packaging structures are designed, fabricated, and measured. Measured results demonstrate that with and without underfill U8410-99 the interconnect return loss is better than 20 and 10 dB from DC to 90 GHz, with an insertion loss of 0.2 and 0.45dB at 60GHz, respectively.

Silicon-correlated Simulation Methodology of EM Side-channel Leakage Analysis

Cryptography hardware is vulnerable to side-channel (SC) attacks on power supply current flow and electromagnetic (EM) emission. This article proposes simulation-based power and EM side-channel leakage analysis (SCLA) techniques on a cryptographic integrated circuit (IC) chip in system level assembly. SCLA measures SC leakage metrics including T-score, SC leakage score, and the number of measurement traces to disclosure, leveraged by a secure system-on-chip design flow toward SC attack resiliency and SC leakage sign off. Power SCLA features the tracking of security sensitive registers within cryptographic logic paths and the automatic assignments of probe points on associated physical power nets. Power supply current traces are efficiently simulated for the large set of input payloads, with direct vector-based and vector-less random switching controls. EM SCLA evaluates magnetic fields created by every piece of metal wiring in metal stacks where power supply current of cryptographic processing flows. The EM emission and EM SCLA from the backside Si surface of an IC chip in flip-chip packaging are experimentally examined with a 0.13 μm test chip. The proposed simulation-based SCLA exhibits the SC leakage metrics of on-chip location and direction dependency as accurately as in the measurements.