Cost Analysis of Fan-out Processes for Chiplet Packaging

Abstract

When building a design around chiplets, there are many factors to consider: industry standards, availability of chiplets within the supply chain, size requirements, and cost, to name a few. The cost of chiplet packaging is a particularly important factor that must be understood, because even if all design requirements can be met, the chiplet package will not come to fruition if the total cost is too high. The basic tradeoff between a monolithic die and a series of chiplets is a reduction in silicon costs countered by an increase in packaging costs. This analysis will compare a monolithic die flip chip package to two fan-out processes that support chiplet packaging. In the first scenario, a two-chiplet chip-last fan-out on substrate package will be compared to a standard flip chip package. For the second comparison, a monolithic flip chip package will be compared to a four-chiplet fan-out package that utilizes embedded silicon for additional interconnect. For both scenarios, a detailed cost comparison will be provided. Activity based cost modeling will be used for this analysis. In addition to looking at the direct costs of the substrate and assembly processes, yield considerations and the price of the incoming silicon (which varies by node) will be included. The goal of this analysis is to evaluate the cost of a monolithic flip chip package versus a chiplet scenario for two designs, and to highlight the cost drivers of the fan-out chiplet packaging processes.