Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

Abstract

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.