Comparison of Package-on-Package Technologies Utilizing Flip Chip and Fan-Out Wafer Level Packaging

Abstract

Fan-out wafer level packaging (FOWLP) has been an area of focus in the electronics packaging industry for multiple years now. As the technology matures, the number of applications for which FOWLP is suitable is growing. Depending on the application, FOWLP may be competing against wire bond, flip chip, embedded, interposer-based, or 3D stacked technologies. In order to make an informed decision, designers must understand not only the value of FOWLP technology, but the value of the package it seeks to replace. Technical capabilities and final package cost are the two key factors to evaluate when making this decision. This analysis focuses on package-on-package (PoP) technologies. Amkor, TSMC, and STATS ChipPAC are all examples of OSATs and foundries providing FOWLP-PoP solutions. The incumbent technology against which FOWLP-PoP is compared is flip chip packaging with through mold vias, and both process flows will be discussed. A cost and yield analysis is carried out to determine the cost implications of different design attributes, and activity based cost modeling is used. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The goal of this analysis is to understand the costs associated with variations of the FOWLP-PoP process, and to evaluate the design attributes that play a role in determining whether FOWLP-PoP or FC-PoP has the potential to be cost-effective.