Flip Chip Package Research Articles

Finite element analysis of thermal distributions of solder ball in flip chip ball grid array using ABAQUS

PurposeThe increased use recently of area‐array technology in electronic packaging has similarly increased the importance of predicting the thermal distribution of area‐array solder interconnection. As the interconnection technology for flip chip package is getting finer and smaller, it is extremely difficult to obtain the accurate values of thermal stresses by direct experimental measurements. Different types of solder bumps used for interconnection would also influence the thermal distribution within the package. Because the solder balls are too small for direct measurement of their stresses, finite element method (FEM) was used for obtaining the stresses instead.Design/methodology/approachThis paper will discuss the results of the thermal stress distribution using numerical method via ABAQUS software. The variation of the thermal stress distribution with the temperature gradient model was evaluated to study the effects of the different material thermal conductivity of solder bumps used. A detailed 2D finite element model was constructed to perform 2D plain strain elastoplastic analysis to predict areas of high stress.FindingsIt is found that thermal distribution of solder bumps starts to propagate from the top region to the bottom region of the solder balls. Other than that, thermal stress effect increases in parallel with the increasing of the temperature. The simulation results shows that leaded solder balls, SnPb have higher maximum thermal stress level compared to lead‐free SAC solder balls.Originality/valueThe paper describes combination of stress with thermal loading correlation on a flip chip model. The work also shows how the different thermal conductivity on solder balls influences the thermal induced stress on the flip chip package.

Thermally and Electrically Enhanced Wirebond BGA

Next-generation processors continue to demand more thermal and electrical performance from the package. Frequently, devices are designed into Flip Chip (FC) packages where the previous generations were in Wire Bond (WB) because FC typically provides superior thermal dissipation and lower package electrical parasitics than WB packages. However, FC packages usually have higher costs for mid-range IO (500–800). An Enhanced WB BGA package has been designed with improved thermal and electrical performance compared to the industry standard TEPBGA-2 (Thermally Enhanced PBGA type 2). The 500μm barrier of mold compound between the die and heatspreader in the TEPBGA-2 is a major impediment to heat flow out of the package. By contrast, the Enhanced WB package uses post-mold attachment of a heat spreader that is adhesively bonded to the mold cap and thermally coupled to the die using a 40μm TIM (thermal interface material). Improvements to substrate design rules and the die attach process that enabled the Enhanced WB design to shorten bond wires by 40% and improved electrical performance. Package thermal resistance, Theta-Ja, was verified by simulation and measurement to be 3C°/W lower than TEPBGA-2, that dissipates up to 15W in some end-use applications, approximately 2× the performance of TEPBGA-2. DDR set-up and hold time showed 30ps improvement by both simulation and measurement. This paper will present the package design, thermal and electrical simulation and measurement results.

Comprehensive Thermomechanical Analyses and Validations for Various Cu Column Bumps in fcFBGA

Since the employment of copper (Cu) column bump (with lead-free solder cap) interconnect offers flexibility in the aspect ratio, increases the I/O density, and provides the characteristic of fine-pitch bumps in flip-chip technology (less than 150 μm bump pitch), a significant amount of research on Cu column bumps in flip-chip packages has been carried out in recent years. For the implementations of Cu column bumps, the architectures of bump-on-capture (BOC) pad with solder bump on pre-solder and bump-on-lead (BOL) with solder bump on Cu trace are usually adopted in flip-chip packages. For the purpose of realizing the mechanical behaviors for fcFBGA (flip-chip fine-pitch ball grid array) with lead-free (LF) bump, Cu column bump, and Cu column bump without (w/o) LF solder cap (Cu column w/o solder cap), this paper presents 3-D finite element analysis (FEA) and compare their warpage and stress responses. The experimental coplanarity measurements for these three types of bumps in fcFBGA are carried out to validate the FEA results. Moreover, the reliability assessment for the underfill selection is further validated with an FEA study. Through validation and simulation, it is observed that the use of an LF bump was better at preventing extreme low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> (ELK) failure and aluminum (Al) pad/underbump metallurgy (UBM) delamination, while the use of Cu column bump with and without a solder cap can avoid pre-solder crack failure. In addition, because the packaging geometry and material always play important roles in determining mechanical behaviors, identifying the most significant factors that affect the stress and warpage responses is useful if stress and warpage reductions in fcFBGA are required. In order to gain the essential factors in fcFBGA, systematic simulation studies for LF bump, Cu column bump, and BOL are illustrated. The impact levels for the top significant factors that influence the ELK, UBM, and bump stresses as well as the warpage are obtained through systematic simulation studies. Several suggestions for reducing warpage and the critical stresses in fcFBGA with Cu column bumps are recommended. The results show that the stresses in ELK, UBM, and bump in the BOL structure are smaller than those in a BOC structure, demonstrating that the BOL structure provides a reliable fcFBGA package without any ELK damage, UBM delamination, or bump crack issues. The perpendicular BOL orientation in the corner bump area also prevents damage that can be caused by a Cu trace or LF bump. It is believed that the proposed results will provide design guidelines to enhance package reliability and reduce the package cost during the development stage.

An overview of molded underfill in flip chip packaging applications

Flip chip packaging is a wide-spread process used in high frequency, high IO count IC devices. It consists of joining the IC chip with the substrate using solder alloys or Cu pillars to form a continuous interconnection for the electronic signals to travel through. However, because during operation these devices dissipate heat, the temperature at the bumps interface rise and drop in cycles which cause thermal stress to build up due to the different thermal expansion of the materials. If left unchecked, these stresses will weaken and eventually cause fatigue failures. Therefore, stress absorbers are dispensed or underfilled to fill the gap between the substrate and the die. Underfills, as these materials are commonly known, are typically dispense as liquids using a variety of techniques like spraying, jetting, injection dispense, etc. In this paper we'll discuss the benefits and challenges of a new type of process that integrates the overall encapsulation of the package with the underfill process in one single process step, called molded underfilling. We'll discuss this application for simple devices consisting of one IC chip and then extend the discussion towards more complex package configurations consisting of IC chips and passive components to demonstrate the flexibility and robustness of this new process solution.

Adhesion and Cure Mechanism Studies for Advanced Lidded Flip Chip Applications

As packages utilizing the next technology nodes increase in power density and end-customers demand more functionality per device, many designs are facing thermo-mechanical and reliability challenges at an unprecedented level. Area array flip chip packages have become the package of choice for many of these advanced devices. These flip chip packages often require a complex arrangement of polymeric, metal, and ceramic components to work together in order to provide such performance, and maintain that performance for a given set of conditions and durations. One important aspect of this symbiosis is the design of the heat dissipation aspects of the package and how it is integrated with the electromechanical aspects of the package –in particular the adhesive technology used for coupling these two components. In this paper, the adhesive material properties are characterized along with the impact on the assembly process as well as on the package reliability.

Thermal modeling approach for enhancing TCNCP process for manufacturing fine pitch copper pillar flip chip packages

Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being primary drivers for devices like smart-phones and tablets. Today solder interconnect pitches, for both low-end and high-end flip chip applications, approximately range from 200μm to 90μm in area array. Advanced silicon nodes create challenges to fine pitch flip chip interconnects and corresponding substrate technology. Fine pitch (&amp;lt;60μm pitch) flip chip (FPFC) packaging is an emerging technology that meets the demand for both smaller form factors and lower cost products. Copper pillar bumps are best suited for fine pitch applications because they allow low standoff height and robust package reliability. Previous feasibility studies show that thermo-compression bonding process with non-conductive paste (NCP) is well suited for manufacturing copper pillar based FPFC packages because the NCP paste encapsulates the bumps and protects the vulnerable die interconnects. TCNCP process can be described as (1) NCP paste is pre-dispensed on a substrate (2) bumped die is picked up by the heater tool (3) proper heating profile and compression load is applied and (4) heater tool detaches and die is allowed to cool. This process requires precise control of temperature and force to get robust flip chip interconnect shape and void-free NCP coverage. TCNCP process has very small heating times usually ranging between 2 to 4 seconds per die. Within such short time, the heater temperature is quickly ramped up to 3 times its initial temperature to melt the solder at the tip of the copper bumps and cure the NCP. Small package layers make it very difficult for the heat to spread quickly. Therefore any temperature gradients within the heater are propagated into the die. Large temperature gradients within the die can potentially introduce manufacturing related challenges like solder “non-wet” and “de-wet”. In this paper these issues are briefly discussed. An experimentally validated thermal model is presented to develop an understanding of rapid heat flow patterns during a typical TCNCP process. Detailed parametric computational study is performed on different die sizes, heating temperature and time to propose a broad guideline on achieving optimal temperature distribution during the TCNCP process.

Electrophoretic Deposition of Carbon Nanotubes for Interconnections in Microelectronics

ABSTRACTCarbon nanotubes (CNTs) have been considered as a promising interconnect material to replace the solder bump used in the flip chip package because of their special electrical, mechanical and thermal properties, which may promote both the performance and reliability of the flip chip packaging. In this paper, electrophoretic deposition (EPD) of CNTs on substrates has been demonstrated for the interconnect application. EPD is a simple, low cost and high throughput process that is capable to produce densely packed film with good homogeneity at low temperature. By altering the electric fields and deposition time during the EPD process, the thickness of the CNTs film could be controlled. In this study, multi-walled carbon nanotubes (MWCNTs) were successfully coated on the various substrates using the EPD method. A highly uniform CNTs microstructure film with thickness over 5 µm was achieved. In addition, the selective depositions of CNTs on the pre-defined bond pads to form CNTs bumps were also accomplished. By employing typical flip-chip bonding technique, high density CNTs bumps were aligned to form a test chip/host substrate interconnects. The electrical conductivity of the CNTs interconnects was carried out using four-point probe measurement. Reliable electrical contacts with linear relationship in the current-voltage (I-V) characteristic suggesting ohmic behaviour were attained. The overall resistances extracted were also relatively low. These superior electrical properties have demonstrated that the CNTs bumps deposited using EPD method is a viable way to serve as an alternative to current metal solder interconnects material such as Sn-Pb alloys. Hence, it offers a promising interconnect application in the quest for device miniaturization in microelectronic industry.

Study on Bump Arrangement to Accelerate the Underfill Flow in Flip-Chip Packaging

Flip-chip packaging is an integrated circuit packaging technique that uses solder bumps to connect chip with substrate. The underfill process uses epoxy encapsulant to solve this problem and improves the reliability of flip-chip packaging. The encapsulant is filled into the gap between the chip and substrate by the capillary force so that the thermal stresses may disperse into the underfill materials to avoid crack generation. The filling time in the underfill process strongly depends on the arrangement of the solder bumps. The edge effect can enhance the filling speed during the underfill encapsulation if the void formation can be avoided. With distributed bump pitch design, the filling time of the underfill can be reduced. There exists an optimal selection of the pitch variation during the use of distributed bump pitch. Another method of using a center bump-free channel can also increase the filling efficiency. The optimization method is used to determine the size of the channel that is found to increase the filling speed dramatically in the case of underfill of the chip with a fine bump pitch.

Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling &amp; Characterization

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

Copper, Nickel, and Lead-Free Solder Electroplating Solutions for Pillar and Micro-Pillar Capping Applications

Control of height-uniformity, morphology, and interfacial properties is critical to achieving high-yield, high-reliability Copper Pillar and Copper Micro-Pillar capped structures for flip-chip and 3D Packaging applications. The plating chemistries selected for electrolytic copper, barrier layer, and lead-free solder deposition significantly affect these properties. A range of copper plating chemistries is evaluated for plating performance and deposit properties for 20um diameter and 75um diameter pillar plating. Height uniformity, pillar shape, surface morphology, and physical properties are compared. These electroplated copper pillars are then evaluated for compatibility with barrier layers and lead-free solder capping. Post-reflow IMC formation, interfacial properties, and micro-voiding phenomena are studied and the effect of the plating chemistry on the overall compatibility of layers in stacked structures is discussed.

Thermal and Mechanical Properties of Flip Chip Package with Au Stud Bump

Thermal and Mechanical Properties of Flip Chip Package with Au Stud Bump

FEM Design and Experiment of XY Motion Platform in Flip Chip Machine

XY motion platform in flip chip machine plays a key module to achieve precise positioning in the process of flip chip packaging. The paper presents an XY motion platform structure. The static and modal characteristics of the XY motion platform were calculated by finite element method, and then some important conclusions were obtained. The displacement and stress distribution of XY motion platform were disclosed. The relevant change trends of displacement and stress under the different load were investigated and the first four natural vibration modes of the XY motion platform were obtained. In the experiment, the vibration behavior was measured by a non-contact laser measuring device. The experiments verify the correctness of the simulation of the XY motion platform. These results can help improve the reliability of the XY motion platform.

Interactions between Variable Frequency Microwave Underfill Processing and High Performance Packaging Materials

Variable frequency microwave (VFM) has been recently proposed as an alternative underfill curing method that provides flip chip package warpage improvement as well as potential underfill cure time reductions. The current paper outlines how such advantages in VFM processing of underfill can be compromised when applied to high performance organic packages. VFM recipes for three underfill materials were developed by performing several VFM curing runs followed by curing rate measurements using the differential scanning calorimetry method. The VFM curing rate was seen to strongly dependent upon the underfill chemistry. By testing flip chip parts that comprised large and high-end substrates, we showed that the underfill material has negligible impact on VFM warpage with the major cause attributed to the coefficient of thermal expansion mismatch between the die and the substrate. Comparison between the convection and the VFM methods indicated two warpage tendencies that depended upon the VFM curing temperature. First, when both curing methods used comparably high temperatures, warpage increases up to about + 20% were found with VFM. This unexpected result was explained by the high-density Cu loading of the substrate which systematically carried heat generated by VFM energy from the die/underfill system to the substrate. Since this high-end substrate consists of sequential dielectric/Cu layers with asymmetric distribution of Cu, additional stresses due to local CTE mismatches between the Cu and the dielectric layers were induced within the substrate processed with VFM. Second, warpage reductions down to about − 22% were obtained at the VFM curing temperature of 110°C with a curing time similar to that of convection cure. This suggests that the negative effect of the local CTE mismatches were no longer at play at the lower VFM temperatures and that the significantly lower final cure temperatures produced lower total shrinkage of the die and the substrate. Finally, due to lower elastic moduli, the cured VFM parts showed better mechanical reliability with no fails up to 1500 cycles.

Adopt Advanced RDL Rule to Apply Flip Chip Technology for Next Generation Si Node: Feasibility Study

With Si node shrinking to 28nm technology, smaller pitch of die pads becomes available so that more IO pads can be layed out. Sometimes the die requires flip chip packaging because of either functionality and performance requirement or cost effectiveness. This paper proposed an advanced RDL solution for a tigher pitch die. A local 10/10um L/S PBO RDL rule is applied to route a die that has three rows staggered 40/80um pitch pads into an area type die, and thermal compression method is used to assembly the chip with flip chip process. Initial construction analysis shows that this is a viable solution.

Package Technology Selection of 28nm High Power FPGA with Pb-Free Solder Bumps: Flip Chip Molded BGA (FCMBGA) versus Traditional Flip Chip Bare Die Package

Selecting the optimal flip-chip package technology for the next generation 28nm FPGA is critical not only to meet reliability benchmarks for Pb-free bumps, but also in meeting the field-use environment requirements for high power devices. Component level reliability testing was conducted on three separate package types: Bare die flip chip BGA (FCBGA), flip chip molded BGA with capillary underfill (FCMBGA w/CUF), and flip chip molded BGA with molded underfill. (FCMBGA). Testing was conducted independently at two separate sites. Testing included moisture resistance testing (MRT), temperature cycle (JESD22-A104 Condition Level B), and a hybrid test combining 100 hours of unbiased HAST (JESD22-A118A) with temperature cycling. Reliability monitoring was conducted through multiple means including electrical testing for circuit continuity, CSAM imaging at frequent read points to monitor silicon integrity and underfill adhesion performance, cross-sections for the inspection of bump crack propagation, and FIB analysis of the UBM structure after test completion. In addition to reliability testing of three flip chip BGA platforms, other usage factors were considered. These include package specific design rule flexibility for passive placement and future generation packaging requirements. The results of the evaluation demonstrated that bump integrity remained strong for all three package types – showing no cracks after 1,500 temperature cycles, hybrid testing, or MRT. Ultimately, the FCMBGA with molded underfill was selected based on the quality of the bumps after testing, the design rule flexibility for capacitor placement, and improved component protection from mechanical damage.

Advanced Microelectronics Packaging Solutions for Miniaturized Medical Devices

The wide range of applications for medical electronics drives unique requirements that can differ significantly from commercial &amp; military electronics. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present report, key enablers for achieving reduction in size, weight, and power (SWaP) in electronic packaging for a variety of medical applications are discussed. Advanced microelectronics packaging solutions with embedded passives are enabling SWaP reductions. Implementation of these solutions has realized up to 27X reduction in physical size for existing PWB assemblies, with significant reductions in weight. Shorter interconnects can also reduce or eliminate the need for termination resistors for some net topologies. Successful miniaturized products integrate the following design techniques and technologies: component footprint reduction, thin high density interconnects substrate technologies, I/O miniaturization and IC assembly capabilities. This paper presents fabrication and electrical characterization of embedded actives and passives on organic multilayered substrates. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on embedded chips, resistors, and capacitors. Embedded passive technology further enhances miniaturization by enabling components to be moved from the surface of the substrate to its internal layers. The use of thin film resistor material allows creating individual miniaturized buried resistors. These resistors provide additional length and width reduction with negligible increases to the overall substrate and module (SiP) height. Resistor values can vary from 5 ohm to 50 Kohm with tolerances from 5 to 20% and areas as small as 0.2 mm2. The embedded resistors can be laser trimmed to a tolerance of &amp;lt;5% for applications that require tighter tolerance. The electrical properties of embedded capacitors fabricated from polymer-ceramic nanocomposites showed a stable capacitance and low loss over a wide frequency and temperature range. A few test vehicles were assembled to do system level analysis. Manufacturing methods and materials for producing advanced organic substrates and flex along with ultra fine pitch assemblies are discussed. A case study detailing the fabrication of a flexible substrate for use in an intravascular ultrasound (IVUS) catheter demonstrates how the challenges of miniaturization are met. These challenges include use of ultra-thin polymer films, extreme fine-feature circuitization, and assembly processes to accommodate die having reduced die pad pitch. In addition, new technologies for embedding a variety of active chips are being developed. A variety of active chips, including a chip having dimensions of one millimeter square, have been embedded and electrically connected to develop high performance packages.

Capillary-driven micro flows for the underfill process in microelectronics packaging

Capillary-driven micro flow allows liquid transport by interfacial force without external pressure or momentum. Theoretical and experimental studies have been conducted to predict the movement of the flow meniscus in the application of capillary underfill flows. In a flip chip package, two-dimensional motions of flow front through solder bumps can result in unwanted air void formation because the meniscus and the arrangement of the solid surface affect the interface dynamics. This study introduces analytical models of filling time and discusses their verification and limitations. Recent developments in underfill flow visualization are also presented to analyze flow phenomena, including the racing effect and void formation.

Stress Analysis under Cu Bump Bonding Process

The copper wire has some advantages in thermal performance, mechanical performance, and low cost, which make it can provide the lowest cost flip-chip(FC) package for low I/O density device. The 2D Cu stud bump finite element model was set up by using ANSYS/LS-DYNA with LOLID162 element to dynamic simulate the Cu stud bump bonding shaping process. The stress distribution in the Cu stud bump and the pad during the bonding process were studied, and the influence of pad thickness on the stress distribution of Si chip was also analyzed. The results shows that under the bonding process the Cu bump height is mainly influenced by the bonding pressure and the top shape of the Cu bump is influenced by ultrasonic energy, the increase of pad thickness results in reducing stress concentration inside the Si chip.

Thermal deformation measurement of flip-chip substrate using digital image correlation method

With the accelerated development of electronic products, flip-chip packaging has become one of the most prominently used and efficient designs in the integrated circuit (IC) industry. In daily application, the IC chip will be subjected to a temperature increase when it is in operation. With the rise in temperature, the chip is liable to a series of deformations which lead to possible malfunction of the IC unit. Therefore, the investigation of thermal deformation of flip-chip substrates is important. In this study, the thermal deformation of flip-chip substrates is measured with dual-camera digital image correlation technology, and with the measured data, a basis is established to predict the warpage conditions and strain tendencies of substrates due to thermal effect. Experiments were carried out with the substrates heated from room temperature to 200°C in a specialized vacuum-sealed oven. The topographic surface profile at higher temperatures can be obtained by adding the measured deformation to the surface profile of the substrates at room temperature. Experimental results show that the center area of the specimen had been warped up around 90 µm from the initial condition and the warpage effect of the substrate is obvious when the temperature increases to 200°C. The related maximum normal and shear strains are also discussed.

IMC의 영향에 따른 Flip-Chip Bump Layer의 열변형 해석

최근 전자 제품의 소형화, 박형화 및 집적화에 따라 칩과 기판을 연결하는 범프의 미세화가 요구되고 있다. 그러나 범프의 미세화는 직경 감소와 UBM의 단면적 감소로 인하여 전류 밀도를 증가시켜 전기적 단락을 야기할 수 있다. 특히 범프에서 형성되는 금속간화합물과 KV의 형성은 전기적 및 기계적 특성에 큰 영향을 줄 수 있다. 따라서 본 논문에서는 유한요소해석을 이용하여 플립칩 범프의 열변형을 분석하였다. 우선 TCT의 온도조건을 통하여 플립칩 패키지의 열변형 특성을 분석한 결과, 범프의 열 변형이 시스템의 구동에 큰 영향을 미칠 수 있음을 확인하였다. 그리고 범프의 열변형 특성에 큰 영향을 미칠 것을 생각되는 IMC층의 두께와 범프의 직경을 변수로 선정하여 온도변화, 열응력 및 열변형에 대한 해석을 수행하였으며, 이를 통하여 IMC층이 범프에 영향을 미치는 원인에 대한 분석을 수행하였다. Recently, by the trends of electronic package to be smaller, thinner and more integrative, fine bump is required. but It can result in the electrical short by reduced cross-section of UBM and diameter of bump. Especially, the formation of IMCs and KV can have a significant affects about electrical and mechanical properties. In this paper, we analyzed the thermal deformation of flip-chip bump by using FEM. Through Thermal Cycling Test (TCT) of flip-chip package, We analyzed the properties of the thermal deformation. and We confirmed that the thermal deformation of the bump can have a significant impact on the driving system. So we selected IMCs thickness and bump diameter as variable which is expected to have implications for characteristics of thermal deformation. and we performed analysis of temperature, thermal stress and thermal deformation. Then we investigated the cause of the IMC's effects.