Flip Chip Package Research Articles

Non-linear analyses of strain in flip chip packages improved by the measurement using the digital image correlation method

Numerical methods like the finite element (FE) method are often used to evaluate the reliability of electronic packages. However, the accuracy of non-linear numerical analyses should be confirmed by experimental measurements. In this study, we evaluated the strain distribution in flip chip (FC) packages with multi-layered printed circuit boards (PCBs) by combining the digital image correlation method (DICM) and the non-linear FE method, considering the viscoelasticity of resins and the elastoplasticity and creep of solder alloy. Four types of FC package consisting of two types of buildup (BU) resin and two types of underfill (UF) resin were evaluated. The distributions of strain on the cutting sections of FC packages were measured using the DICM with microphotographs obtained by a confocal laser scanning microscope (CLSM). The strain measurements showed that the UF resin with the low coefficient of thermal expansion (CTE) reduced thermal strain around a solder bump, and the BU resin with the low CTE reduced the strain concentration along the interface between a Si chip and a solder bump. We performed the non-linear FE analyses while taking into account the viscoelastic Poisson’s ratio of the UF resin and the constant instantaneous Poisson’s ratio. The result of the FE analyses with the constant instantaneous Poisson’s ratio did not correspond with the strain measurements using the DICM. The normal strain in a solder bump was less than that obtained by the measurement, and the direction of a shear strain band in a solder bump was different from that measured using the DICM. On the other hand, the FE analyses considering the viscoelastic Poisson’s ratio showed good agreement with the strain measurements using the DICM. The strain measurement using the DICM improved the accuracy of the non-linear FE analysis of microelectronic packages effectively.

Using BP network for ultrasonic inspection of flip chip solder joints

Flip-chip technology has been used extensively in microelectronic packaging, where defect inspection for solder joints plays an extremely important role. In this paper, ultrasonic inspection, one of the non-destructive methods, was used for inspection of flip chip solder joints. The image of the flip chip was captured by scanning acoustic microscope and segmented based on the flip chip structure information. Then a back-propagation network was adopted, and the geometric features extracted from the image were fed to the network for classification and recognition. The results demonstrate the high recognition rate and feasibility of the approach. Therefore, this approach has high potentiality for solder joint defect inspection in flip chip packaging.

Effects of Hardeners on the Low-Temperature Snap Cure Behaviors of Epoxy Adhesives for Flip Chip Bonding

Various adhesive materials are used in flip chip packaging for electrical interconnection and structural reinforcement. In cases of COF(chip on film) packages, low temperature bonding adhesive is currently needed for the utilization of low thermal resistance substrate films, such as PEN(polyethylene naphthalate) and PET(polyethylene terephthalate). In this study, the effects of anhydride and dihydrazide hardeners on the low-temperature snap cure behavior of epoxy based non-conductive pastes(NCPs) were investigated to reduce flip chip bonding temperature. Dynamic DSC(differential scanning calorimetry) and isothermal DEA(dielectric analysis) results showed that the curing rate of MHHPA(hexahydro-4-methylphthalic anhydride) at <TEX>$160^{\circ}C$</TEX> was faster than that of ADH(adipic dihydrazide) when considering the onset and peak curing temperatures. In a die shear test performed after flip chip bonding, however, ADH-containing formulations indicated faster trends in reaching saturated bond strength values due to the post curing effect. More enhanced HAST(highly accelerated stress test) reliability could be achieved in an assembly having a higher initial bond strength and, thus, MHHPA is considered to be a more effective hardener than ADH for low temperature snap cure NCPs.

Highly Reliable and Manufacturable Ultrafine Pitch Cu–Cu Interconnections for Chip-Last Embedding With Chip-First Benefits

Flip-chip packaging of Ultrafine pitch integrated circuits aggravates the stress-strain concerns as the interconnection pitch is decreased, requiring a fundamentally different system approach to interconnections, underfill processes and interfaces, and the substrate. This paper demonstrates an innovative and manufacturable solution to achieve excellent reliability at Ultrafine pitch (~30 μm) using direct copper-copper (Cu-Cu) interconnections with adhesives. A number of 30-μm bump pitch test vehicles (TVs) were designed with 3 mm × 3 mm chips to extract both daisy chain resistance and single-bump resistance data. Assembled bump resistivity was found to be ~ 3-4× lower than most solders. Performance of these TVs was studied for high temperature storage (HTS) life test, unbiased-highly accelerated stress test (U-HAST) and thermal cycling test (TCT). Test results showed that the assemblies with this next generation interconnection technology depicted excellent reliability results in HTS, U-HAST, and TCT tests. Based on these results, it is concluded that adhesive materials, provide unique opportunities for Ultrafine pitch and high performance interconnections.

Alternating reaction phases in Sn–Cu/Ni–Co solid-state reactions

This study investigates Sn–Cu/Ni–Co solid-state interfacial reactions to evaluate Ni–Co alloys as new diffusion barrier layer materials for flip chip packaging of Cu/low-k chips. Sn–Cu alloys are promising lead-free solders. In Sn–Cu/Ni–20at%Co interfacial reactions, after 115h reaction, the reaction phases are CoSn2/Ni3Sn4. After 720h reaction, the reaction phases are CoSn2/Ni3Sn4/CoSn2/Ni3Sn4. An unusual alternating reaction phase phenomenon, CoSn2/Ni3Sn4/CoSn2/Ni3Sn4/CoSn2/Ni3Sn4/CoSn2/Ni3Sn4, is found after 1006h reaction. This alternating phenomenon is attributed to the small mobility of Ni in comparison with Sn and Co. In Sn–Cu/Ni–40at%Co interfacial reactions, only Sn and Co are dominant diffusion species, and their mobilities do not differ significantly. Only CoSn2 and CoSn3 single layers are formed. The alternating phenomenon is not observed.

Packaging and Non-Hermetic Encapsulation Technology for Flip Chip on Implantable MEMS Devices

We report here a successful demonstration of a flip-chip packaging approach for a microelectromechanical systems (MEMS) device with in-plane movable microelectrodes implanted in a rodent brain. The flip-chip processes were carried out using a custom-made apparatus that was capable of the following: 1) creating Ag epoxy microbumps for first-level interconnect; 2) aligning the die and the glass substrate; and 3) creating non-hermetic encapsulation (NHE). The completed flip-chip package had an assembled weight of only 0.5 g significantly less than the previously designed wire-bonded package of 4.5 g. The resistance of the Ag bumps was found to be negligible. The MEMS micro-electrodes were successfully tested for its mechanical movement with microactuators generating forces of 450 μN with a displacement resolution of 8.8 μm/step. An NHE on the front edge of the package was created by patterns of hydrophobic silicone microstructures to prevent contamination from cerebrospinal fluid while simultaneously allowing the microelectrodes to move in and out of the package boundary. The breakdown pressure of the NHE was found to be 80 cm of water, which is significantly (4.5-11 times) larger than normal human intracranial pressures. Bench top tests and in vivo tests of the MEMS flip-chip packages for up to 75 days showed reliable NHE for potential long-term implantation.

Packaging Effects of Multiple X-Band SiGe LNAs Embedded in an Organic LCP Substrate

Interconnects in radio frequency (RF) packages have a strong tendency to deteriorate RF performance, especially in high-frequency systems. In this paper, comparison is made between the wirebonded and embedded flip-chip packages. X-band silicon-germanium low-noise amplifiers are used to evaluate the performance of these interconnects. Measured results show that the embedded flip-chip packages have better RF performance than the wirebonded packages for X-band applications. At 9.5 GHz, the flip-chip interconnects contribute only 0.4 dB of insertion loss, while the wirebond interconnects contribute 2.2 dB of insertion loss. The flip-chip and wirebond interconnects are modeled and validated against measured results from 8 to 20 GHz. For the first time, multiple dies are put together in a single liquid crystal polymer package to compare the packaging effects, and to demonstrate the feasibility of embedding multiple dies within a single package for highly integrated solutions.

Norris–Landzberg Acceleration Factors and Goldmann Constants for SAC305 Lead-Free Electronics

Goldmann constants and Norris–Landzberg acceleration factors for SAC305 lead-free solders have been developed based on principal component regression models (PCR) for reliability prediction and part selection of area-array packaging architectures under thermo-mechanical loads. Models have been developed in conjunction with stepwise regression methods for identification of the main effects. Package architectures studied include ball-grid array (BGA) packages mounted on copper-core and no-core printed circuit assemblies in harsh environments. The models have been developed based on thermomechanical reliability data acquired on copper-core and no-core assemblies in four different thermal cycling conditions. Packages with Sn3Ag0.5Cu solder alloy interconnects have been examined. The models have been developed based on perturbation of accelerated test thermomechanical failure data. Data have been gathered on nine different thermal cycle conditions with SAC305 alloys. The thermal cycle conditions differ in temperature range, dwell times, maximum temperature, and minimum temperature to enable development of constants needed for the life prediction and assessment of acceleration factors. Goldmann constants and the Norris–Landzberg acceleration factors have been benchmarked against previously published values. In addition, model predictions have been validated against validation datasets which have not been used for model development. Convergence of statistical models with experimental data has been demonstrated using a single factor design of experimental study for individual factors including temperature cycle magnitude, relative coefficient of thermal expansion, and diagonal length of the chip. The predicted and measured acceleration factors have also been computed and correlated. Good correlations have been achieved for parameters examined. Previously, the feasibility of using multiple linear regression models for reliability prediction has been demonstrated for flex-substrate BGA packages (Lall et al., 2004, “Thermal Reliability Considerations for Deployment of Area Array Packages in Harsh Environments,” Proceedings of the ITherm 2004, 9th Intersociety Conference on Thermal and Thermo-mechanical Phenomena, Las Vegas, Nevada, Jun. 1–4, pp. 259–267, Lall et al., 2005, “Thermal Reliability Considerations for Deployment of Area Array Packages in Harsh Environments,” IEEE Trans. Compon. Packag. Technol., 28(3), pp. 457–466., flip-chip packages (Lall et al., 2005, “Decision-Support Models for Thermo-Mechanical Reliability of Leadfree Flip-Chip Electronics in Extreme Environments,” Proceedings of the 55th IEEE Electronic Components and Technology Conference, Orlando, FL, Jun. 1–3, pp. 127–136) and ceramic BGA packages (Lall et al., 2007, “Thermo-Mechanical Reliability Based Part Selection Models for Addressing Part Obsolescence in CBGA, CCGA, FLEXBGA, and Flip-Chip Packages,” ASME InterPACK Conference, Vancouver, British Columbia, Canada, Jul. 8–12, Paper No. IPACK2007-33832, pp. 1–18). The presented methodology is valuable in the development of fatigue damage constants for the application specific accelerated test datasets and provides a method to develop institutional learning based on prior accelerated test data.

Underfill process for two parallel plates and flip chip packaging

Two parallel plates with a dimension of 5mm×5mm and various gap heights (5, 10, 15, 20, 25, 30, and 35μm) are simulated using a finite volume method-based software. A three-dimensional model is constructed, and a non-Newtonian underfill flow is simulated using computational fluid dynamics. The flow front advancement is monitored using the volume of fluid model. The underfill process for the two parallel plates and effect of gap height are the main focuses, and the application of flip chip packaging with a gap height of 30μm is studied. The gap height has a crucial influence on the filling time and pressure drop. The presence of solder bumps is found to have a significant effect on the flow pattern at the melt flow portion. The comparison of the simulation and analytical results are in good conformity for the underfill flow of the two parallel plates.

Effect of Nano-Particles on Heterogeneous Void Nucleation in No-Flow Underfill Materials

The large number of voids induced by the thermal effect from solder reflow process is one of the technical challenges for flip chip package techniques typically with no-flow underfills. The underfill voids could extensively reduce the life cycle in thermal cyclic test. This paper reviewed classical heterogeneous bubble nucleation theories to model voids nucleation occurring on the phase boundary of solid solder and liquidus underfill to control the nucleation during flip chip assembly process using no-flow underfill materials. On the heterogeneous voids nucleation, the properties of nucleation sites (such as density and surface tension) that determine void formation were explored using nano-sized fillers. Thus, this experiment investigated the effect of nano-sized fillers, which are potential nucleation sites in the no-flow underfill material, on the void formation by changing the nano-sized filler type and concentration. Eventually, we proposed a formulation guideline of no-flow underfill materials using nano-sized fillers to effectively prevent the underfill voiding during flip chip assembly process.

Conductivities and curing properties of electron-beam-irradiated anisotropic conductive films

Radiation-curable acrylated epoxy oligomer was irradiated by using an electron beam (E-beam) with dosages of 5, 10, 20, 40, 80, 200, 400, and 550 kGy to investigate the electrical and the physical properties of anisotropic conductive films (ACFs) and to evaluate the potential application of radiation technology to flip-chip package processing. An ACF is an insulating epoxy matrix containing conducting particles that keep the electrical conductivity along the out-of-plane direction and the insulation property along the in-plane direction. The contact resistance between ACF joints cured by using an E-beam irradiation of 80 kGy was measured under a constant bonding pressure of 2 kgf/cm2 to demonstrate the effects of pad pitch size and the number of added conductive particles in the epoxy resin. Three types of PCBs, 1000-, 500-, and 100-µm pad pitches, were employed while the E-beam curable epoxy resin was mixed with conductive particles in a weight ratio of 10:1. The measured average contact resistance was 0.24 Ω with a minimum of 0.06 Ω for the samples prepared with a 100-µm pad pitch size, which is compatible with or lower than the values obtained from thermally-cured commercial ACFs. Our results demonstrate that an E-beam is an effective radiation method for curing epoxy resins at low temperatures in a short time and can be employed as a new technique for bonding circuits in high-density electric devices.

Dielectric-Free Fabrication of Compact 30-GHz Photodetectors Using the Isolated Pedestal Contact Configuration

We demonstrate a rapid fabrication process for high-speed waveguide-based photodetectors operating above 30 GHz. The process requires no dielectric planarization, and forms planar ground-signal-ground (GSG) contacts, which is more robust and ideally suitable for flip-chip packaging.

Structural design guideline to minimize extreme low-k delamination potential in 40 nm flip-chip packages

Flip-chip packages with a 40nm wafer node with ELK (extreme low-k) dielectric are prone to early low-k delamination beneath the solder joints right upon flip-chip bonding before underfilling. The chip-package interaction (CPI) therefore becomes a design consideration for flip-chip packages with a 40nm wafer node and beyond. In this work, finite element analyses were carried out to explore CPI in process of a 40nm ELK flip-chip package with SnAg solder joints. Results indicate that a small ratio of polyimide (PI) opening over under bump metallurgy (UBM) size, a thick redistribution layer (RDL) or RDL sandwiched with PI for stress buffering, a thick substrate core, and a thin die are directions to follow in order to minimize the ELK delamination potential.

Testing of Copper Pillar Bumps for Wafer Sort

Using a copper pillar interconnect in flip chip packaging provides a lead-free solution that is more reliable, and also scalable to very fine pitch. Vertical probe card technology, also called buckling beam technology, was used in characterization of wafer probe process and electrical contact on solder bumps and copper pillars at 150 μm pitch arrays. Probe contact was investigated by modeling the scrub, penetration or deformation on a bump under various conditions of wafer probe and experimentally tested on wafers on copper pillars, solder bumps of different metallurgies or sheet wafers. A single-probe contact test system was devised to study the contact behavior of a probe on a bump. Various probe tip geometries including wedge, pointed and flat, were studied. Probing procedures were investigated for achieving reliable electrical contact for large pitch area array bumps as well as fine pitch, 50 μm, copper pillar array bumps using two different wafer test technologies.

An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs

The flip-chip package is introduced for modern integrated circuit (IC) designs with higher integration density and larger I/O counts. In this paper, we consider the pre-assignment flip-chip routing problem with predefined connections between driver pads and bump pads. This problem has been shown to be much more difficult than the free-assignment one, but is more popular in real-world designs because the connections between driver pads and bump pads are typically predetermined by IC or packaging designers. Based on the concept of routing sequence exchange, we propose a very efficient approach to guide the global routing by computing the longest common subsequence and the maximum planar subset of chords for pre-assignment flip-chips. We observe that the existing work over-constrains the capacity of a routing tile, which might miss some critical solution space with a better routing solution (e.g., smaller wirelength), and provide a remedy for this insufficiency to identify a better solution in a more complete solution space. We also develop a constant-time routability analyzer to check if a given set of wires can pass through a tile. Experimental results show that our router can achieve a 125× speedup with even better solution quality (same routability with slightly smaller wirelength), compared with a state-of-the-art flip-chip router based on integer linear programming.

Chip–Package Interaction and Reliability Improvement by Structure Optimization for Ultralow-$k$ Interconnects in Flip-Chip Packages

Mechanical failures in low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> interlayer dielectrics and related interfaces during flip-chip-packaging processes have raised serious reliability concerns. The problem can be traced to interfacial fracture induced by chip-package interaction (CPI). During the packaging processes, thermal stresses arise from the mismatch in coefficient of thermal expansion between the chip and the substrate, which can be directly coupled into the Cu/low-k interconnect structure to drive interfacial delamination. In this paper, finite-element method is used to evaluate the crack driving force induced by CPI and to examine its impact on the reliability of Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> interconnects for 45-nm technology and beyond. First, the characteristics of CPI are investigated for flip-chip packages using a 3-D multilevel global-to-local modeling method where the crack driving force for the interfacial delamination in Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> interconnect structures is evaluated. The effects of dielectric and packaging materials are examined for different low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectrics and Pb-based and Pb-free solders. This study is then extended to explore the potential of using structural optimizations to improve the CPI reliability as the technology continues with dimensional scaling and implementation of porous ultralow- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> materials.

Multiscale, Multiphysics Model of Underfill Flow for Flip-Chip Packages

In this paper, the effects of various conditions on underfill flow including the substrate surface, temperature-dependent underfill properties, nonuniform bump patterns (e.g., missing columns), irregular bump shapes (e.g., slanted bumps), and filler particle redistribution are investigated for flip-chip packages. Experimental studies are first presented for underfill flow in silicon dies with different types of substrate surfaces (ceramic versus organic). Results show that the underfill material cannot wet organic packages well compared to their ceramic counterparts. This is also observed in simulations employing a 2-D global underfill flow model for an isothermal underfilling process. The effects of missing bump columns, temperature-dependent underfill viscosity and surface tension, and irregular bump shapes on underfill flow-out time, flow front shape, and void formation are then investigated in detailed underfill flow models, with each factor resulting in ±4~7% variation in underfill filling time. Finally, the influence of filler particle inhomogeneity due to settling and shear migration is modeled using a full 3-D particle suspension model. The simulated filler particle distribution around solder bumps agrees well with the cross-sectional images of cured underfill samples.

Numerical Simulations of Electromigration and Stressmigration Driven Void Evolution in Solder Interconnects

Understanding the effect of high current density on void formation and growth and relating the size of the void to the resulting electrical/mechanical failure is a critical need at the present time to ensure reliable functioning of flip-chip packages. In general, toward this end, the modeling and simulation of geometrical evolution of current induced voids have been relatively few. Simulations considering the coupled effects of mass transport through mechanisms of surface and bulk diffusion under the influence of electrical, thermal, and stress fields in solder joints leading to eventual electromigration failure do not appear to be common. In this study, we develop a phase field model for the evolution of voids under electrical, thermal, and stress fields in a flip-chip solder interconnect. We derive the equations of motion for the void accounting for energetic contributions from the active factors of surface energy, stress, and electric potential, considering both surface diffusion and transfer of the material through the bulk of the material. We describe the implementation of this model using a finite element code written in the PYTHON language, coupled with a commercial finite element solver from which we obtain the electrical, thermal, and stress fields driving the void motion. We demonstrate the implemented methodology through simulations of void evolution in flip-chip solder joints under the effects of mechanical/electrical fields and surface/bulk diffusion.

Measurement and Analysis for Residual Warpage of Chip-on-Flex (COF) and Chip-in-Flex (CIF) Packages

A flip-chip package using adhesive interconnection consists of materials which have different coefficients of thermal expansion (CTE). The package experiences temperature higher than room temperature during the assembly process and is also exposed to the thermal cycling load during its lifetime. As a result, flip-chip packages have residual warpage after completion of the assembly process. Excessive warpage causes various reliability problems. Therefore, residual warpage is an essential factor for evaluating the reliability of electronic packages. In this paper, we evaluated the warpage of chip-on-flex (COF) packages using the moiré methods. A chip-in-flex (CIF) package developed to increase the binding force between the chip and the substrate was also evaluated with the same methods. Finite element analysis (FEA) was also performed for comparison with the experimental results. Based on the FEA result, effective design parameters for the CIF package were found to reduce the residual warpage.

Effect of stacking chips and inlet positions on void formation in the encapsulation of 3D stacked flip-chip package

The current study investigates the effects of increasing the number of stacking chips and applying three types of inlet positions to the void formation in three-dimensional (3D) stacked flip-chip packaging. A scaled-up single integrated circuit packaging was performed, and the mechanism of void formation was studied throughout the experiment. The entrapment of air was visualized clearly in the experiment because of the unstable flow front during encapsulation. In the 3D stacked flip-chip packaging, the Castro–Macosko model with curing effect was written into user-defined functions and incorporated into the FLUENT software to describe the behavior of the molding compound. The increase in the number of stacking flip-chips increased the void in the package, which tended to form at the stacking chips region. Moreover, the application of three different inlet positions, namely, typical, diagonal, and top center inlets, significantly influenced the flow mechanism and void concentration. Knit lines were identified at the interface between the flows that occurred in the encapsulation. The current modeling also predicted the conversion of the compound. The simulation and experimental results were validated, thus proving that the current virtual modeling could handle the problems during encapsulation excellently.