Structural design guideline to minimize extreme low-k delamination potential in 40 nm flip-chip packages

Abstract

Flip-chip packages with a 40nm wafer node with ELK (extreme low-k) dielectric are prone to early low-k delamination beneath the solder joints right upon flip-chip bonding before underfilling. The chip-package interaction (CPI) therefore becomes a design consideration for flip-chip packages with a 40nm wafer node and beyond. In this work, finite element analyses were carried out to explore CPI in process of a 40nm ELK flip-chip package with SnAg solder joints. Results indicate that a small ratio of polyimide (PI) opening over under bump metallurgy (UBM) size, a thick redistribution layer (RDL) or RDL sandwiched with PI for stress buffering, a thick substrate core, and a thin die are directions to follow in order to minimize the ELK delamination potential.