UBM integrity studies on copper/low-k dielectrics for fine pitch flip chip packaging

Abstract

Technological demands require electronic modules to be faster and highly miniaturized in the coming years. Over the last two decades widely used chip metallization has been aluminum and its alloys of aluminum such as AICu or AISiCu. Development of dual damascene copper metallization processes especially for processors and memories has shown promising performance. As the processor speed increases continuously, more usage of new polymeric low-k dielectric materials to enhance the performance in Cu chip has taken place in last few years [1,2]. The Intemational Technology Roadmap for Semiconductors (ITRS) has identified the UBM(Under Bump Metallurgy) integrity and underfill compatibility as a key area of challenge in the Cu/low-k integrated circuits assembly & packaging [3]. The impact of UBM integrity in Cu metallization has been reported [4] and the major failure mechanism observed is UBM metal peeling from low-k dielectric. However Investigations with different UBM metallization and failure analysis of UBM with copper metallization process particularly with low-k dielectrics is lacking. The objective of this study is to investigate the flip chip packaging characterization with low-k dielectric material used in dual damascene copper integrated circuits. This paper focuses on electroless NdAu, Cu/Ta/Cu and Ti/Ni(V)/CdAu UBM fabricated on 200” damascene Cu wafers and its flip chip package reliability with Pb-free solders. Bump shear test is carried out to evaluate the bump integity and the failures are analyzed through optical and electron microscopy. In order to investigate the thermal stability of UBM system with Ph-free solder, high temperature aging (at above melting temperature) is performed and the interface between solder and UBM is observed with optical and electron microscopy respectively.