Chip–Package Interaction and Reliability Improvement by Structure Optimization for Ultralow-$k$ Interconnects in Flip-Chip Packages

Abstract

Mechanical failures in low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> interlayer dielectrics and related interfaces during flip-chip-packaging processes have raised serious reliability concerns. The problem can be traced to interfacial fracture induced by chip-package interaction (CPI). During the packaging processes, thermal stresses arise from the mismatch in coefficient of thermal expansion between the chip and the substrate, which can be directly coupled into the Cu/low-k interconnect structure to drive interfacial delamination. In this paper, finite-element method is used to evaluate the crack driving force induced by CPI and to examine its impact on the reliability of Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> interconnects for 45-nm technology and beyond. First, the characteristics of CPI are investigated for flip-chip packages using a 3-D multilevel global-to-local modeling method where the crack driving force for the interfacial delamination in Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> interconnect structures is evaluated. The effects of dielectric and packaging materials are examined for different low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectrics and Pb-based and Pb-free solders. This study is then extended to explore the potential of using structural optimizations to improve the CPI reliability as the technology continues with dimensional scaling and implementation of porous ultralow- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> materials.