Flash Memory Array Research Articles

Modeling of $V_{\rm th}$ Shift in nand Flash-Memory Cell Device Considering Crosstalk and Short-Channel Effects

A threshold-voltage (Vth) shift of sub-100-nm NAND flash-memory cell transistors was modeled systematically, and the modeling was verified by comparing with the data from measurement and 3-D device simulation. The Vth shift of the NAND flash-memory cell was investigated by changing parameters such as gate length, width, drain voltage, dielectric material between cells, space between cells, lightly doped-drain depth, and adjacent-cell bias. The proposed model covers two dominant device physics: capacitance coupling effect between adjacent cells and short-channel effect. Our model showed an accurate prediction of the Vth shift of NAND flash-memory array and a good agreement with the data from simulation and measurement.

테라비트급 나노 스케일 SONOS 플래시 메모리 제작 및 소자 특성 평가

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of , 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

Explanation of SILC Probability Density Distributions With Nonuniform Generation of Traps in the Tunnel Oxide of Flash Memory Arrays

In this paper, we develop a detailed physical model to interpret the dependence of the stress induced leakage current (SILC) distributions on the nature and position of the generated defects, and we exploit it to reconsider in detail previously published experimental data on the statistical distribution of the SILC in Flash arrays. We found that a unique symmetrical spatial distribution of traps, which is rapidly decreasing from the Si-SiO2 interfaces toward the center of the oxide, can explain the oxide-thickness and stress-level dependence of the measured SILC distributions. The generation of cooperating defects with increasing stress time is also analyzed and discussed.

Impact of Pulsed Operation on Performance and Reliability of Flash Memories

We tested the impact of pulsed operation (PO) on standard NOR flash memory arrays. PO is a new writing scheme featuring a sequence of ultrashort high-voltage pulses based on Fowler-Nordheim (FN) tunneling. This paper presents experimental results showing a significant improvement on both performance and reliability of Flash memory arrays using PO which include smaller standard deviation of the threshold-voltage distribution, less tail bits, and less cycling-induced tunnel oxide degradation. Measurements reveal also that a specific array design taking into account for both wordline and substrate parasitic capacitances can further increase the benefits deriving from the use of PO. The proposed PO writing scheme is suitable for all floating gate memories using FN tunneling as writing mechanism.

Vertical Flash Memory Cell With Nanocrystal Floating Gate for Ultradense Integration and Good Retention

We demonstrate a new vertical (3-D) Flash memory transistor cell with nanocrystals as the floating gate on the sidewalls that can form a high-retention ultrahigh density memory array. This scalable vertical cell architecture can allow a theoretical maximum array density of 1/(4F 2), where F is the minimum lithographic pitch, thus circumventing the integration density limitations of conventional planar Flash memory arrays. Discrete SiGe nanocrystals that are grown by conformal chemical vapor deposition process on the pillar sidewalls form the floating gate and render excellent retention properties at room temperature and at 85 degC. The cell shows a large memory window of ~1 V and endurance of more than 105 cycles

Single Event Effects in NAND Flash Memory Arrays

We are showing for the first time the charge loss due to heavy ion irradiation on Flash memory arrays organized following the NAND architecture. Results complement those previously found for devices featuring a NOR architecture: large charge loss can be expected after the hit of a single ion on a single memory cell. The resulting threshold voltage shift DeltaVTH grows with ion LET and with applied electric field across the tunnel oxide (that is, with the programming conditions) and cannot be explained by simple generation-recombination-transport models. Further, in Floating Gates hit by a single ion a percolation path develops across the tunnel oxide, able to slowly discharge the Floating Gate

Experimental Characterization of Statistically Independent Defects in Gate Dielectrics—Part II: Experimental Results on Flash Memory Arrays

In this paper we applied the statistical model for independent defects described in Part I, to experimental data measured on Flash memory arrays. The model, developed to describe the stress-induced leakage current (SILC) statistics, allowed us to study the oxide trap generation during program/erase (P/E) stress and to extract the discrete probability distribution (DPD) of the gate current increase due to the single oxide defect. For all the analyzed nonvolatile memory arrays and for all the P/E stresses, the experimental results are consistent with the simulations carried out in Part I, thus confirming the reliability of the statistical model and of its validation procedure. Measurements on Flash cell arrays with different oxide thickness show that the number of generated oxide traps increases linearly with the number of P/E cycles in the early stage of the stress. It is shown, for the first time, that the extracted DPD of the single-trap exhibits long tails with power law dependence on the trap current and with a slope of the tail that decreases with decreasing oxide thickness. These tails are responsible for the cells with the largest SILC values in the Flash memory arrays.

Experimental Characterization of Statistically Independent Defects in Gate Dielectrics—Part I: Description and Validation of the Model

A general statistical model to describe the generation of statistically independent defects in gate dielectrics is presented. In this first paper, the general model, suitable for different types of defects, is developed to describe the stress-induced oxide traps and the statistical properties of the trap-assisted tunneling current (TAT). With our model, it is possible to study the stress-induced leakage current statistics on large Flash memory arrays, to extract information about the number of generated defects, and to reconstruct the probability density distribution (PDD) of the gate current due to the single trap. We validated the statistical model by means of a Monte Carlo simulator developed to describe the oxide trap generation and the TAT statistics in large Flash memory arrays. In Part II, we applied the statistical model to experimental data measured on Flash memory arrays and we verified the possibility of studying, with our model, the trap generation dynamics and the PDD of the gate current produced by the single oxide defect.

Charge loss after /sup 60/Co irradiation of flash arrays

Flash memories are the most important among modern nonvolatile memory technologies. We are showing new results on the threshold voltage shifts in Flash memory arrays after /sup 60/Co irradiation. A (relatively) high total dose, exceeding 100 krad (SiO/sub 2/), is needed to induce errors in the array, but threshold voltage shifts are all but negligible even at lower doses. These shifts can be accurately described by using a model which considers the charges generated by irradiation in all the oxides surrounding the floating gate. We are also showing that cycling (endurance) and total ionizing dose effects mutually add.

Defect Generation Statistics in Thin Gate Oxides

We analyze data-retention experiments for flash memory arrays with thin tunnel oxide (t/sub ox/ = 5 nm). These samples show an additional conduction mechanism besides Fowler-Nordheim tunneling and stress-induced leakage current (SILC). The additional leakage contribution is analyzed with respect to the spatial distribution in the array and the shape of the current-voltage characteristics, and is interpreted as an anomalous SILC due to a two-trap leakage path. From the cycling dependence of the distribution tails related to one- and two-trap leakage, we provide evidence that the defect generation statistics is not Poissonian, but is instead correlated. Possible physical mechanisms responsible for correlated generation are also discussed.

Impact of Correlated Generation of Oxide Defects on SILC and Breakdown Distributions

A three-dimensional Monte Carlo model for analysis of the reliability of flash memory arrays is developed, and applied to thin tunnel oxide (t/sub ox/ = 5 nm) samples. Good agreement between experimental data and simulation results are obtained, assuming a correlated defect generation in the tunnel oxide of our samples as evidenced in (Ielmini et al., 2004). The impact of correlated defect generation on dielectric breakdown is also addressed by means of a percolation model. It is shown that correlated generation provides no significant degradation of the breakdown lifetime with respect to Poisson statistics.

Statistical profiling of SILC spot in flash memories

A new experimental technique for evaluating the position of the oxide weak spot responsible for the stress-induced leakage current (SILC) in flash memories is presented. The oxide field along the channel is modified by drain biasing, and the gate current is then monitored. The position of the leakage spot can be determined by the shift in the gate current-voltage (I-V) characteristics. Experimental results on flash memory arrays reveal a strong localization of SILC in correspondence of the drain junction, due to the cooperation effects of program/erase (P/E) operations. The technique can be used to optimize the P/E conditions for maximum device reliability.

Advanced salicided 4 Mbit flash memory array with borderless contacts

System on chip development requires many different devices to be integrated on the same chip and a high compatibility between CMOS logic core process and added modules. The self-aligned silicide process coming from high performance logic gives in a Flash memory array several opportunities: to take advantage of low word-line resistance, to eliminate any metal strap in the array reducing potential process defectivity thus improving devices yield. On the other hand, the salicidation of Flash memory requires at the same time to achieve a continuous low resistance line on the no-flat array topography (due to the double poly stacked gate memory cell structure) and to avoid any junction leakage risk, that might modify the device performances. The aim of this work is to demonstrate the feasibility and compatibility of advanced Ti salicide process with Flash memory array embedded in a high performance logic. The feasibility has been proven on a classical NOR 4 Mbit stand-alone memory test chip processed in 0.25 μm technology, that furthermore asks for borderless contacts.

Bandwidth optimization of flash memories with the RGP technique

A simple expression for the number of bits that can be programmed per unit time (bandwidth or BW) in flash memories with the ramped gate programming (RGP) technique is used to optimize memory BW and derive design curves. Preliminary experimental results obtained with common-ground NOR flash memory arrays realized with 0.25 /spl mu/m technology show that memory BW can: (1) exceed of 10 Mb/s with optimized cell programming and (2) be negatively affected by device scaling.

Low voltage flash memory by use of a substrate bias

The enhancement of the gate current in MOSFET devices by use of a substrate bias has been explained by a second impact ionization event at the drain-to-substrate junction. Hot electron luminescence measurements confirm this interpretation showing that only the high-energy tail of the electron distribution is affected by the substrate bias. This phenomenon has been applied to a FLASH memory array to increase the injection efficiency. Low voltage and good control of disturbs has been demonstrated in a 0.5 Mbit embedded FLASH array using substrate bias during programming.