Abstract
A general statistical model to describe the generation of statistically independent defects in gate dielectrics is presented. In this first paper, the general model, suitable for different types of defects, is developed to describe the stress-induced oxide traps and the statistical properties of the trap-assisted tunneling current (TAT). With our model, it is possible to study the stress-induced leakage current statistics on large Flash memory arrays, to extract information about the number of generated defects, and to reconstruct the probability density distribution (PDD) of the gate current due to the single trap. We validated the statistical model by means of a Monte Carlo simulator developed to describe the oxide trap generation and the TAT statistics in large Flash memory arrays. In Part II, we applied the statistical model to experimental data measured on Flash memory arrays and we verified the possibility of studying, with our model, the trap generation dynamics and the PDD of the gate current produced by the single oxide defect.
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