Abstract
A simple expression for the number of bits that can be programmed per unit time (bandwidth or BW) in flash memories with the ramped gate programming (RGP) technique is used to optimize memory BW and derive design curves. Preliminary experimental results obtained with common-ground NOR flash memory arrays realized with 0.25 /spl mu/m technology show that memory BW can: (1) exceed of 10 Mb/s with optimized cell programming and (2) be negatively affected by device scaling.
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