FinFET Process Research Articles

Fraction of Insertion of the Channel Fin as Performance Booster in Strain-Engineered p-FinFET Devices With Insulator-on-Silicon Substrate

The combined impact of process- and substrate-induced stress has been analytically modeled for a rectangular fin inserted into an insulator-on-silicon (IOS) substrate. Stress estimation and profiling are performed for different fractional insertion of the fin into the IOS substrate and the induced stress values are observed to saturate for ≥1/3 of the fin insertion. Therefore, a one-third of inserted Si fin is used to estimate the induced stress by following a standard FinFET process flow. Uniaxial compressive stress as high as 4.6 GPa has been obtained, and it has also been observed that the hole mobility can be enhanced to a significantly high value by judiciously choosing the gate dielectrics and fractional insertion of the fin. Thereby, the design of symmetric CMOS by using such mobility-enhanced p-FinFET is possible. Moreover, the current–voltage characteristics of such strain-engineered p-FinFETs exhibit improved drain-induced barrier lowering and subthreshold swing and ~45% enhancement of drain current.

Investigation of BTI characteristics and its behavior on 10 nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack

Bias-Temperature Instability (BTI) is one of the key device reliability concerns for both digital and analog circuit operations. Features of work-function metal (WFM) for VT modulation in 10nm FinFET process technology results in WFM dependent BTI characteristics. Similar levels of aging degradation to those of previous 14nm technology were observed in both DC and AC operations. As BTI-induced VT variability is expected to increase with 3D fin dimension scaling, such variability must be accurately characterized and considered for circuit designs. This paper reports the impact of transistor- level BTI degradation on circuits by studying Ring Oscillator (RO) and SRAM. The SRAM cell stabilities in terms of SNM (Static Noise Margin) and WRM (Write Margin) were further studied through SRAM HTOL stresses by characterizing Vmin shift. Robust 10nm SRAM and product level HTOL reliability up to 500h were demonstrated.

Zen: An Energy-Efficient High-Performance $\times $ 86 Core

AMD's next-generation, high-performance, energy-efficient ×86 core, Zen, targets server, desktop, and mobile client applications with a 52% instructions per clock cycle (IPC) uplift over the previous generation. The increase in IPC complements a 15% process neutral reduction in CAC (switching capacitance). Performance and energy efficiency are further improved with various circuit techniques including write wordline boost, contention-free dynamic logic, supply droop detection with mitigation, a per-core frequency synthesizer, and a per-core integrated linear voltage regulator. Utilizing a 14 nm FinFET process, the Zen core complex unit consists of a shared 8 MB L3 cache and four cores.

Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation

As the semiconductor process technology continuously scales down, circuit delay variations due to manufacturing and environmental variations become more and more serious. These delay variations are hardly predictable and thus require an additional design margin, which impedes the chance to reduce the area and power consumption of a chip. One of the best solutions to alleviate this problem is to measure circuit delays at run time and control the supply voltage accordingly through a closed-loop dynamic voltage and frequency scaling (DVFS) scheme. The key issue of this scheme is the delay mismatch between the monitoring circuit and the target block. A large delay mismatch might lose the advantage of the closed-loop DVFS. It becomes much worse as a circuit block operates in wider voltage range, from near-threshold voltage to super-overdrive voltage. This paper proposes novel delay monitoring systems with multiple generic monitors for wide voltage range operation, which provide a better delay correlation between the monitoring circuit and the target block compared to conventional monitoring approaches. The proposed approaches reduce the maximum error by up to 91% for a popular processor core in a 14-nm FinFET process technology, thereby bring a decrease of design margin, lower-power, and/or lower-cost design.

A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design

With continued scaling of VLSI circuits, reliability has emerged out as one of the major circuit design challenges. Systematic die-to-die, random on-die as well as temperature and supply voltage variations are major sources of performance degradation which leads to unreliable circuits. Further, with reduced short channel effects at highly scaled nodes, the FinFET has recently been emerged as a suitable replacement of CMOS in the VLSI industry. Wide fan-in FinFET domino logic OR gate is one such circuit, which serves as an integral part of register file in a high-speed FinFET microprocessor. This circuit inherently suffers from low noise immunity which get worsens with circuit parameter variations due to process and temperature variations. At highly scaled technology nodes, it has been studied that the effects of on-die random process variation surpass the effects of systematic variations. Furthermore, at deep sub-nanometer scale the effect of process variation on device parameters is higher in FinFET as compared to CMOS. In this research work a reliable current mirror-based wide fan-in FinFET domino OR gate is proposed for temperature, random on-die and systematic die-to-die process variation tolerance. Simulation results at 32 nm FinFET process show that the proposed design is capable of maintaining high noise immunity (Unity Noise Gain of nearly 0.4 V) at all process corners and a constant performance (with reduced delay by 30% as compared to conventional design) in the presence of systematic as well as random process and temperature variations.

Novel tri-independent-gate FinFET for multi-current modes control

In this paper, a novel tri-independent-gate (TIG) FinFET is presented for multi-current modes control for the first time. The entire integration flow of proposed TIG FinFET is fully compatible with the mainstream gate-first HKMG FinFET process. Five kinds of ON state modes and threshold voltages can be offered by TIG FinFET without additional voltage sources, and it is demonstrated to have a great potential in dynamic voltage SRAM design. The critical electrical parameters of TIG FinFET in different modes are fully investigated with TCAD simulation and compared to the traditional FinFET. TIG FinFET with double fins is found to possess a distinct different output and capacitance characteristics with single fin FinFET. The underlying physical mechanisms are analyzed and investigated in detail.

Charge-Steering Latch Design in 16 nm FinFET Technology for Improved Soft Error Hardness

A charge-steering based latch hardening technique with very low performance tradeoff and significant SEU hardness is presented. Mixed-mode 3D-TCAD simulations are used to illustrate the effect of charge steering in reducing the amount of collected charge at the critical sensitive nodes. Circuit simulations also highlight that the tradeoffs in terms of area, speed and power penalties are much lower compared to other hardening approaches, such as hysteresis and spatial-redundancy techniques. Alpha particle, heavy-ion, and proton test results for circuits designed in a 16 nm FinFET process indicate significant SEU hardness, comparable to DICE FF design, for low LET particles.

A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET

A 3-tap 64 Gb/s NRZ transmitter using a quad-rate architecture is designed in 16 nm FinFET. The design incorporates circuit techniques and topologies that take into account device properties specific to FinFET process. A 4:1 MUX consisting of static CMOS pulse generators and a tailless CML multiplexing stage is used at the final stage of serialization. An on-chip regulator provides power to the pulse generators and CMOS clock buffers. A phase error correction circuit corrects the phase errors of the four-phase clocks generated by an LC-PLL. The transmitter achieves 800 mV-ppd with 150 fs RJ while consuming 225 mW at 64 Gb/s.

Advanced Wet Clean Technology at Lightly Doped Drain Layers in FinFET

Along with fast-paced development of semiconductor industry, circuit patterns become much smaller and finer. Currently the pattern design migrates from traditional planar structure to three-dimensional FinFET. Therefore how to remove surface particles in various sizes effectively without damaging the pattern structures in the higher aspect ratio is more and more essential to achieving critical rapid yield ramps in the advanced technology node. In the FinFET process scheme, after formation of poly gate, Lightly Doped Drain (LDD) implants are invented to alleviate the short channel effect between Source and Drain Junction. In LDD layers, low density impurity of B+ and As+are implanted into PFET and NFET, respectively. The repeated implant steps will inevitably bring certain amount of surface particles, which are defined in higher killer ratio, since they can be embedded defect after few nitride spacer layers are deposited, causing the poor device performance and low product yield. Figure 1 shows the typical SEM images of various surface particles generated during repeated LDD implant steps. Standard RCA Clean 1 (SC1) with the mixture of hydrogen peroxide, ammonium hydroxide and deionized water usually would be applied to reduce organic and surface particle. But particles removal efficiency (PRE) is not satisfied for advanced FinFET manufacturing. Aerosol or nanospray to dispense chemical solution with the mixture of nitrogen gas in high pressure is another candidate to possess higher PRE, however, the traditional aerosol technique would create liquid droplets in a large range of size, so the non-uniformed momentum of liquid droplet can result in severe pattern damage on poly gate at LDD layers. In this paper, we report an advanced wet clean method based a single wafer clean toolset. By using this state-of-the-art wet clean technology, we can control the size and velocity of liquid droplets accurately during the clean chemical dispense. In this sense, with high PRE for surface particles, in the meantime, there is no sacrifice of gate pattern damage in LDD layers. It was demonstrated on FinFET production wafers that surface particles were reduced by as much as 30% with the new clean technology implementation. Also, about 5% yield improvement was observed for the new clean process. Figure 1: Typical SEM images of surface particle defect in LDD layers Figure 1

Scaling Trends for Picojoule-per-Bit WDM Photonic Interconnects in CMOS SOI and FinFET Processes

This paper presents a link analysis for optical interconnects based on CMOS scaling toward FinFET devices. An on-chip wavelength division multiplexing (WDM) link is modeled assuming silicon photonic ring modulators, WDM multiplexers and demultiplexers, and photodetectors. A high-speed CMOS transceiver is designed and evaluated using 28-nm FD-SOI and 14-nm FinFET processes. Compared to 28-nm FD-SOI, the 14-nm FinFET offers higher intrinsic gain and allows for 50% higher transconductance per drain current suggesting more energy-efficient circuit design. Cosimulation of the photonic and electronic devices demonstrates an optimum energy efficiency of $\sim 2\, \text{pJ/b}$ at $25\, \text{Gb/s}$ for a bit-error rate of $10^{-12}$ including laser and ring tuning power.

Titanium-Oxide-Based Slot Contact RRAM in Nanoscaled FinFET Logic Technologies

In this letter, a new ultrahigh-density memory constructed with a contact resistive random access memory (RRAM) is proposed. This slot contact RRAM (SCRRAM) with transition metal oxide from contact liner layers has been successfully demonstrated by a standard 16-nm FinFET process without extra mask or processing step. The new FinFET RRAM features low-power forming and reset operation, stable Low Resistance State (LRS)/High Resistance State (HRS), and compact cell size. As a logic nonvolatile memory (NVM) solution, SCRRAM exhibits high endurance, stable data retention, read and program disturb immunity, which further support this new 1T1R cell as one of the promising embedded NVM solutions in FinFET CMOS generations.

Contact Chains for FinFET Technology Characterization

Electrical characterization remains a key element in technology development and manufacturing of integrated circuits. Contact chain is a well known part of the diagnostic set of test structures used across many generations of silicon processes. Implementation of such test structures becomes challenging in new technologies with 3-D devices, like FinFET. Contacts to active regions of such devices are inherently dependent on the architecture of epitaxial raised source and drain and for proper characterization require the presence of transistor gates, which set the environment for contacts. This paper describes a new type of test structure, so-called gated contact chains, developed for contact process characterization in FinFET technologies. Instead of simple chain of contacts, each structure contains a series of active devices with common gate electrode used to turn on the chain of transistors to enable measurement of chain resistance. To discriminate between chain failures caused by an open contact or by other mechanisms (e.g., bad transistor with very high threshold voltage) a series of measurement under various test conditions was performed and analysed. In order to overcome a limitation of the contact chain size and enable data collection from larger sample of contacts, we proposed to implement the gated chains in addressable arrays, increasing their density and failure rate observability. Finally, the paper presents the examples of electrical failure modes detected by those chains in FinFET process.

Novel 14-nm Scallop-Shaped FinFETs (S-FinFETs) on Bulk-Si Substrate.

In this study, novel p-type scallop-shaped fin field-effect transistors (S-FinFETs) are fabricated using an all-last high-k/metal gate (HKMG) process on bulk-silicon (Si) substrates for the first time. In combination with the structure advantage of conventional Si nanowires, the proposed S-FinFETs provide better electrostatic integrity in the channels than normal bulk-Si FinFETs or tri-gate devices with rectangular or trapezoidal fins. It is due to formation of quasi-surrounding gate electrodes on scalloping fins by a special Si etch process. The entire integration flow of the S-FinFETs is fully compatible with the mainstream all-last HKMG FinFET process, except for a modified fin etch process. The drain-induced barrier lowering and subthreshold swing of the fabricated p-type S-FinFETs with a 14-nm physical gate length are 62 mV/V and 75 mV/dec, respectively, which are much better than those of normal FinFETs with a similar process. With an improved short-channel-effect immunity in the channels due to structure modification, the novel structure provides one of possibilities to extend the FinFET scalability to sub-10-nm nodes with little additional process cost.

Characterization of metal contact to III–V materials (Mo/InGaAs)

The CMOS device channel material for sub-10nm dimensions has been identified to be major challenge as per the International Technology Roadmap for Semiconductors (ITRS). Among the options that are defined by ITRS roadmap is the high mobility III–V based channels. In this paper, we report on new III–V materials showing great potential in achieving nanometric scale transistors in support of applications that require operating at 0.3–0.5V. In the first phase of this research, a special focus was given to Molybdenum/InGaAs contacts in order to set up basic unit processes and characterization techniques. Indeed, the electrical measurement were performed and linked to the interface morphology characterized by Scanning Electron Microscopy (SEM), Scanning Transmission Electron Microscopy (STEM) and High Resolution Transmission Electron Microscopy (HRTEM). Kelvin structures of Molybdenum over InGaAs were fabricated as test structures to measure the contact resistance and resistivity of the aforementioned interface. Plasma damages induced during the fins definition by reactive ion etching are known to significantly increase the contact resistivity in III–V based finFET. The digital etch technique is implemented on an unexposed plasma damages sample in order to assess the compatibility of this technique with a finFET process flow. The first set of electrical measurements gives a contact resistance of 0.71Ωμm2 competitive with existing Mo/InGaAs contact resistance, revealing the compatibility of the digital etch cleaning technique with common MOSFET process flow.

InGaAs Gate-All-Around Nanowire Devices on 300mm Si Substrates

In this letter, we present the first InGaAs gate-all-around (GAA) nanowire devices fabricated on 300mm Si substrates. For an L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> of 60 nm an extrinsic g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> of 1030 μS/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> = 0.5 V is achieved which is a 1.75× increase compared with the replacement fin FinFet process. This improvement is attributed to the elimination of Mg counterdoping in the GAA flow. Ultrascaled nanowires with diameters of 6 nm were demonstrated to show immunity to D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> resulting in an SS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> of 66 mV/decade and negligible drain-induced barrier lowering for 85-nm L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> devices.

Addressing FinFET metrology challenges in 1× node using tilt-beam critical dimension scanning electron microscope

At 1× node, a three-dimensional (3-D) FinFET process raises a number of new metrology challenges for process control, including gate height and fin height. At present, there is a metrology gap in inline in-die measurement of these parameters. To fill this metrology gap, in-column beam tilt has been implemented on Applied Materials V4i+ critical dimension scanning electron microscope for height measurement. Low-tilt (5 deg) and high-tilt (14 deg) beam angles have been calibrated to obtain the height and the sidewall angle information. Evaluation of its feasibility and production worthiness is done with applications in both gate height and fin height measurements. Transmission electron microscope correlation with an R2 equal to 0.89 and a precision of 0.81 nm have been achieved on various in-die features in a gate height application. The initial fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to greater challenges brought by the fin profile, yet it is promising for the first attempt. Sensitivity to design of experiment offset die-to-die and in-die variations is demonstrated in both gate height and fin height. The process defect is successfully captured with inline gate height measurement. This is the first successful demonstration of inline in-die gate height measurement for a 14-nm FinFET process control.

(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations

We introduce SiGe FinFET device physics, process integration, and modeling considerations. Germanium is know to have a higher hole mobility than silicon. Enhancement of hole velocity due to lattice mismatch strain in SiGe epitaxy layers is significant. In addition, uniaxial stress is beneficial for device performance. Transformation of biaxial to uniaxial stress naturally occurs when SiGe film is etched into stripes. Furthermore, control of MOSFET threshold voltage by adjusting the SiGe-channel germanium content is possible. On the other hand, SiGe processing challenges include the elimination of interface trap states at the gate dielectric interface, fast diffusion of n-type dopants, and defects in stress relaxed buffer and critical thickness limitations. Band-to-band tunneling sets a lower bound to device static leakage current.

(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations

We introduce SiGe MOSFET process integration and device impact from a simulation perspective. Germanium is know to have a higher channel hole mobility. Enhancement of hole velocity due to lattice mismatch strain in shilicon germanium epitaxial layers is significant. Processing challenges include the elimination of interface trap states at the dielectric interface, fast diffusion of n-type dopants, defects in stress relaxed buffer and critical thickness limitations. Uniaxial stress is beneficial for device performance. Transformation of biaxial stress to uniaxial is natural when etching silicon germanium into stripes. From a device perspective, silicon germanium is useful for shifting MOSFET device Vth.

FinFET Devices and Integration

FinFET Devices and Integration

(Invited) A Comparison of Device Architecture, Electrical Performance and Process Flow between FinFET and Planar MOSFETs

In this paper, we compared the device architecture, electrical performance between bulk planar, SegFET, UTBB-SOI and FinFET MOSFETs based on TCAD simulation and we also listed the key fabrication process difference between bulk planar and FinFET devices. Results show that FinFET has best short channel effect (SCE) immunity due to its double gate structure. Hence, FinFET device demonstrates best DC performance, which includes Ion/Ioff, Sub-threshold Swing and DIBL. Analyses also show FinFET has best AC performance: smallest delay and dynamic power consumption. Besides some 20nm technology node’s processes, some brand new processes, such as Fin formation, low-k spacer, poly and HK/MG CMP, SiC/SiGe in-situ doping with Ti-silicide and SAC local interconnects, need to be introduced into the FinFET process flow as a necessary cost of achieving the superior performance.