Fine-pitch Ball Grid Array Research Articles

Undissolved gold in fine-pitch BGA solder joint under thermal cycling test

Undissolved gold in fine-pitch BGA solder joint under thermal cycling test

ILP-based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design

With the rapidly growing demand for system-level integration, package substrates have become one of the most important carriers in semiconductor industry. Fine pitch ball grid array (FBGA) packaging is a widely used technology thanks to its relative cost-effectiveness compared to other advanced packaging technologies. In addition, it is also widely used in space-constrained applications, such as mobile and handheld devices. These packaging substrate interconnections are usually customized by layout engineers taking many complex and stringent design rules into consideration. However, fully net-by-net manual design for FBGA is time-consuming and error-prone. In this article, we propose an integer linear programming (ILP)-based router for wire-bonding FBGA packaging design. Our ILP formulation not only can handle design-dependent constraints but also take the problem of mismatched via dimension into account, which is caused by the mechanical processes and greatly increases design complexity. In addition to the ILP formulation for substrate routing, three optimization stages and several ILP constraint reduction techniques are also developed to boost the run time of ILP solver. Experimental results indicate that the proposed framework can achieve high routing completion rates, which could effectively reduce the cycle time of substrate layout design. In addition, in combination with the proposed optimization strategies, 278× speedup can be achieved compared to the ILP constraint optimized router.

An open-source UFBGA µ-board for wearable devices

This paper presents the development of an open-source, low-sized, BGA microcontroller breakout board, that can be used for the development of wearable and cyber-physical prototypes. The board is based on the low power, 8-bit, ATtiny20-CCU Microchip AVR microcontroller. The ATtiny20-CCU can be programmed without bootloader, using the Atmel Tiny Programming Interface (TPI), instead of In-System Programming (ISP). The C code used to program the microcontroller can be written and compiled using the Microchip Studio freeware platform. The ATtiny20-CCU Ultra Fine-pitch Ball Grid Array (UFBGA) packaging technology allows the shrinkage of the conceived Electroless Nickel-Immersion Gold (ENIG) Printed Circuit Board (PCB) to a size of only 15.5 × 13 mm. Its low cost also makes it a viable option for developing many educational electronic projects, especially for Instrumentation and Assistive Technology. The contribution of this paper is mainly the hardware prototype design, the PCB manufacturing, building and test of a very low-sized open source µ-breakout PCB board, for wearable Instrumentation applications, towards the emergent Society/Industry 5.0.

Parametric study of thermally induced warpage of FpBGA package using finite element methods

Warpage is considered to be the major concern in ensuring the reliability and manufacturability of electronic package because a flat package is crucial for a successful formation of board level assembly process. Warpage is the out of plane displacement which is a resultant of difference in co-efficient of thermal expansion (CTE) between the adjoining packaging materials. Enormous warpage may lead to occurrence of faulty joints such as open connections, mis-shaped joints, and loss of package board-level reliability under manufacturing, thermal loading process, shock and vibration. In this paper, a Fine pitch ball grid array Package (FpBGA) which is a prominent type of electronic package offering solution for downsizing of electronic components such as mobiles and camcorders has been choose for study. Warpage of FpBGA was simulated from post cure temperature to reflow temperature using Finite Element Methods. A static thermal analysis was carried out using ABAQUS software and a parametric study was done to investigate the effect of material properties and geometric properties in minimizing the warpage. Materials properties such as CTE, Elastic modulus of substrate and die, geometric properties like thickness of die and substrate were chosen for study.

DDR4 BER Degradation Due to Crack in FBGA Package Solder Ball

This paper measures bit error rate degradation in DDR4 due to crack in fine pitch ball grid array (FBGA) package solder ball. Thermal coefficient mismatch between the package and printed circuit board material causes cracks to occur in solder balls. These cracks change the electrical model of the solder ball and introduce parallel capacitance in the electrical model. The capacitance causes higher frequency attenuation and closes the data eye. As the data rate of the DDR4 increases there are more data eye closures. The data eye closure causes bit error rate (BER) degradation as the timing margin and voltage margin decreases. This degradation reduces the reliability of the system and causes more intermittent errors. DDR4 data line is loaded with a parallel capacitive element to mimic a crack in solder ball. The measured data eye shows a decrease in eye width. Bathtub plots are created for comparison of cracked solder ball and intact solder ball. The bathtub plots show the BER degradation due to crack in solder ball.

Study on Delamination Between Polymer Materials and Metals in IC Packaging Process.

The electronic package interconnects electronic signals from one area to another and package delamination is a serious problem in the configuration of materials. This study focused on decreasing the delamination of the low-profile fine pitch ball grid array (LFBGA) and plastic ball grid array (PBGA) packages in terms of polymer thermal issue, metal bonding and bonding mechanisms. PBGA and LFBGA are a very common type of packaging processes in the electronics industry. The present study dealt first with delamination of the LFBGA packaging, through characterization and determination of physical and chemical properties such as surface roughness, surface energy, and contact angle. The relationship between surface roughness and delamination was verified through various roughness bonding experiments. In addition, the surface energy was determined by measuring the contact angle after cleaning the metal surface of Cu, Ni and Cr with Ar + O2 gas, and, this gas plasma treatment was applied to enhance the adhesive properties. The compositions of the surface were analyzed through an X-ray photoelectron spectroscopy (XPS). Also, the delamination issue between the corner of the heat sink cap and the epoxy resin was observed for delamination of the LFBGA packaging. Further, this study analyzed the PBGA packaging process through the finite element analysis simulation software ANSYS. To improve the heat sink cap delamination issue of the PBGA, a new chamfer design of the corner seat was streamlined to decrease the stress value and delamination. Besides, the simulation results demonstrated that the stress value reduced after increasing the shoulder length. The results implicate that the stress value is inversely proportional to the shoulder width and the chamfer radius. This study demonstrated that the optimization in design was able reduce the delamination phenomena in configuration material.

A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller

A 4266Mb/s/pin LPDDR4 interface with an asynchronous feedback continuous-time linear equalizer (AF-CTLE) and an adaptive 3-step eye detection algorithm for memory controller is presented. The AF-CTLE removes the glitch of DQS without training by applying an offset larger than the noise, and improves read margin by operating as a decision feedback equalizer in DQ path. The adaptive 3-step eye detection algorithm reduces power consumption and black-out time in initialization sequence and retraining in comparison to the 2-D full scanning. A prototype chip was implemented in a 65-nm CMOS process with fine-pitch ball grid array package and tested with commodity LPDDR4 memory. The write margin was 0.36 UI and 148 mV; and the read margin was enhanced from 0.30 UI and 76 mV without AF-CTLE to 0.47 UI and 80 mV to with AF-CTLE. The power efficiency during burst write and read were 5.68 pJ/bit and 1.83 pJ/bit, respectively.

Flip-Chip (FC) and Fine-Pitch-Ball-Grid-Array (FPBGA) Underfills for Application in Aerospace Electronics—Brief Review

In this review, some major aspects of the current underfill technologies for flip-chip (FC) and fine-pitch-ball-grid-array (FPBGA), including chip-size packaging (CSP), are addressed, with an emphasis on applications, such as aerospace electronics, for which high reliability level is imperative. The following aspects of the FC and FPGGA technologies are considered: attributes of the FC and FPBGA structures and technologies; underfill-induced stresses; the roles of the glass transition temperature (Tg) of the underfill materials; some major attributes of the lead-free solder systems with underfill; reliability-related issues; thermal fatigue of the underfilled solder joints; warpage-related issues; attributes of accelerated life testing of solder joint interconnections with underfills; and predictive modeling, both finite-element-analysis (FEA)-based and analytical (“mathematical”). It is concluded particularly that the application of the quantitative assessments of the effect of the fabrication techniques on the reliability of solder materials, when high reliability is imperative, is critical and that all the three types of research tools that an aerospace reliability engineer has at his/her disposal, should be pursued, when appropriate and possible: experimental/testing, finite-element-analysis(FEA) simulations, and the “old-fashioned” analytical (“mathematical”) modeling. These two modeling techniques are based on different assumptions, and if the computed data obtained using these techniques result in the close output information, then there is a good reason to believe that this information is both accurate and trustworthy. This effort is particularly important for high-reliability FC and FPBGA applications, such as aerospace electronics, as the aerospace IC packages become more complex, and the requirements for their failure-free operations become more stringent.

Simulation study on thermo-fatigue failure behavior of solder joints in package-on-package structure

In this work, the simulating analysis of PoP structure under the temperature range from 0°C to 125°C is carried out using direct thermal-cycle analysis and Coffin-Manson method. The results show that the maximum accumulating inelastic hysteresis energy appears on the solder ball in the bottom fine-pitch ball grid array (FBGA) structure. The thermal-fatigue crack initiates in the two symmetrical corners of solder ball in FBGA structure. The thermal-fatigue damage evolves fast in the outer row corner's balls then slowly propagates into the inner row balls in FBGA structure. By analyzing the failure data of solder balls, a thermal-fatigue failure criterion is defined where the critical failure probability value is about 80%.

Reliability of SAC 105 and SAC1205N under Drop Tests

Abstract In this paper, the solder joint failure and the solder joint fatigue life in the Thin-profile Fine-pitch Ball Grid Array (TFBGA) Package was investigated by performing the drop test, and implementing a simulation model. Owing to the need to meet the increasing demands for functionality, microelectronic package reliability can be compromised and has become the key issue when executing drop tests. During impact in drop test, the deformation of PCB due to bending and mechanical shocks can cause solder joint crack. While this is a well-known issue, observing the solder joint responses during the test execution can be a challenge. Therefore, in this work, a simulation model approach has been developed to investigate the stress and strain of the solder joint during the drop test. In this research, the JEDEC Condition B drop test was simulated, characterized by 1500G peak acceleration and 0.5 ms duration. The drop test simulation model was successful in predicting the solder joint fatigue life with different solder joint materials, such as SAC105 and SAC1205N, while also facilitating result comparison to identify the most optimal structure.

B-Spline X-Ray Diffraction Imaging — Rapid non-destructive measurement of die warpage in ball grid array packages

Next generation “More than Moore” integrated circuit (IC) technology will rely increasingly on the benefits attributable to advanced packaging (www.itrs.net[1]). In these increasingly heterogeneous systems, the individual semiconductor die is becoming much thinner (25 to 50μm, typically) and multiple dies can be stacked upon each other. It is difficult to assess non-destructively, non-invasively and in situ the stress or warpage of the semiconductor die inside these chip packages and conventional approaches tend to monitor the warpage of the package rather than the die.This paper comprises an account of a relatively new technique, which we call B-Spline X-Ray Diffraction Imaging (B-XRDI) and its application, in this instance, to the non-destructive mapping of Si semiconductor die lattice misorientation inside wire bonded encapsulated Low-profile Fine-pitch Ball Grid Array (LFPGA) packages. B-XRDI is an x-ray diffraction imaging technique which allows the user to reconstruct from a series of section x-ray topographic images a full profile of the warpage of the silicon semiconductor die inside such a chip package. There is no requirement for pre-treatment or pre-processing of the chip package and we show that synchrotron-based B-XRDI mapping of wafer warpage can be achieved with angular tilt resolutions of the order of 50μrad≈0.003° in times as short as 9–180s (worst case X–Y spatial resolution=100μm) for a full 8.7mm×8.7mm semiconductor die inside the fully encapsulated LFBGA packages. We confirm the usefulness of the technique by correlating our data with conventional warpage measurements performed by mechanical and interferometric profilometry and finite element modelling (FEM). We suggest that future developments will lead to real-time, or near real-time, mapping of thermomechanical stresses during chip packaging processes, which can run from bare wafer through to a fully encapsulated chip package.

Evaluation about Solder-IMC Crack of Fine Pitch BGA Package

FBGA is widely adopted as AP and memory package for mobile devices such as a smart phone and a smart watch. FBGA is attached to PCB assembly during SMT process. Double side SMT is preferred to increase the battery area for slim design and long life of mobile device. Solder-IMC crack is in-process reliability failure occurs during 2nd side SMT. The buried via is often used in double side SMT PCB is filled with filler material of CTE is highly mismatched to surrounding PCB laminates (FR-4). Tensile stress is applied to BGA pad by this CTE mismatch at high temperature and causes the solder-IMC crack. In this paper, we evaluate the factors of solder-IMC crack related to PCB and BGA. It is found that the length of buried via related to PCB thickness influences the solder-IMC crack. But if the location of buried via is not aligned to the location of BGA pad, solder-IMC crack does not occur. In the case of buried via and BGA pad are aligned each other, the failure rate of solder-IMC crack can be lowered by controlling O2 level that is less than 1000ppm and by applying solderball with high Ag content for SAC alloy. The temperature cracking solder-IMC interface is measured. The result shows that the solder-IMC crack occurs before solder joints are fully melted. The solder joint with low Ag content having broad melting temperature range is relatively weaker than high Ag having near eutectic point. It is recommended to design the PCB with buried via which avoids the location of the BGA pad and this is the good solution to reduce the failure rate of solder-IMC crack to near zero.

Characteristics of a System in a Package with Silver Wires

The system in a package (SiP) including of a system on a chip (SoC) and a double-data-rate-three synchronous dynamic random access memory (DDR3 SDRAM) were studied with respect to the high-speed characteristics. The SiP was the multi-chip-module thin-profile fine-pitch ball grid array (MCM TFBGA) package with four-layer substrate. The high-speed 1600-Mbps data rate DDR3 signals were used in the signal integrity (SI) analysis. The SiP with low-cost silver (Ag) wires displayed a 500.18-ps aperture width in the eye diagram, which was successfully achieved signal integrity (SI) performance requirement. This work demonstrated the SiP with the Ag wires was the great potential solution for the advanced high-speed product applications.

Reliability Comparison of Aged SAC Fine-Pitch Ball Grid Array Packages Versus Surface Finishes

Pb-free solder joints exposed to elevated isothermal temperatures for prolonged periods of time undergo microstructural and mechanical evolution, which degrades the joint electrical performance. We report the effect of isothermal aging on the reliability of Sn–Ag–Cu (SAC) assemblies on three different surface finishes [immersion Ag (ImAg), electroless Ni/immersion Au (ENIG), and electroless Ni/electroless Pd/immersion Au (ENEPIG)]. The characteristic life for SAC alloys in 10- and 15-mm ball grid array packages on ImAg degraded over 40% after an 85 °C/12 months aging and over 50% during a 125 °C/12 months aging. ENIG and ENEPIG outperformed ImAg for all aging treatments. For passive components (2512 resistors) on ImAg, the reliability performance degraded 16.7%/28.1% after a 1-year aging at 85 °C/125 °C. Failure analysis showed dramatic intermetallic binary Cu–Sn and ternary Ni–Cu–Sn film growth at the bottom of the solder joint interfaces for ImAg and ENIG/ENEPIG. For 125 °C-aged samples, the cracks appeared at the corners of both package and board sides of the solder ball and propagated along (near) the intermetallic compound location. For the case of aged fine-pitch packages, the failures tended to start at the component side solder ball corner and then propagate along an angled path downward into the bulk solder.

Optimum conditions of molding VFBGA chips with very minimal gold wire damage using the Taguchi methods

This study employed the analysis of mean (ANOM) of the Taguchi methods to determine the optimal conditions for the very fine pitch ball grid array (VFBGA) transfer molding of a microelectronic assembly with the aim of minimizing wire damage. The optimal conditions include: (1) a substrate preheat temperature of 177°C, (2) two-step mold clamping in which the clamping force in the first-stage is 9t and the full clamping force in the second-stage is 28t, (3) a mold temperature of 180°C, and (4) a total of 20 vacuum holes in the bottom mold. Experiments to confirm the efficacy of the optimal conditions indicated that the average percentage of samples with wire damage was reduced to 0.02%. The percentage contribution of each controllable factor in the current investigation was also determined via ANOVA (analysis of variance) of the Taguchi methods. Among the four controllable factors, the number of vacuum holes in the bottom mold proved to be the one with the greatest influence on wire damage with a percentage contribution of 71.25%. We also describe the mechanism underlying wire damage associated with vacuum holes. Our findings led us to modify the existing VFBGA process, wherein the maximum defect percentage per sub-lot was decreased from 1.31% to 0.12%, and the average defect percentage in 14 sub-lots was decreased from 1.10% to 0.03%.

Optimal design of fatigue life for RCP with PoP package by using the Taguchi method

SummaryIn recent years, the electronic industries tend to offer products with smaller scales, lower cost, larger storage space and integration of various functions. The development of redistributed chip package (RCP) technology is facilitated to reduce package size for three‐dimensional integration and to enhance packaging capability for miniature requirements. Meanwhile, the logic unit is required to be combined with the memory unit to achieve miniaturization and system integration.The RCP with package on package (PoP) is constructed by stacking the RCP for the very fine pitch ball grid array at topside and the stack package ball grid array (SPBGA) at bottom side. The finite element software ANSYS is adopted in this study using the Global/Local modeling approach. The reliability of the RCP with PoP is subjected to a thermal cycle test of ‐40‐125 °C based on JEDEC specification. The Coffin‐Manson strain‐based model and the Morrow energy‐based model are employed for prediction of package fatigue life, in which the SAC387 (95.5Sn3.8Ag0.7Cu) solder joints are treated as viscoplastic behavior according to the Anand constitutive model. The other materials are modeled as elastic behavior.To investigate the solder joint reliability for the stacked package design, a numerical experiment by means of the single factor analysis is first conducted for investigation. The material factors such as Young's Modulus and coefficient of thermal expansion, the geometric factors such as component thickness are evaluated. Accordingly, the significant factors are filtered and analyzed by the Taguchi method to obtain the optimal combination. As a result, the optimal design increases package fatigue life, which contributes a significant improvement by up to 86.5% when comparing with the original model.Copyright © 2014 John Wiley & Sons, Ltd.

Effects of temperature and strain rate on mechanical behavior of low-silver lead-free solder under drop impact

This study uses finite element program to simulate the process of board-level drop for portable electronic devices, so as to create very-thin-profile fine-pitch BGA packages model. Based on the data from quasi-static tests and the experimental data measured by split Hopkinson pressure bar, the parameters of Cowper–Symonds model about solder joints were obtained, taking into consideration of strain rate effect and temperature effect. The results show that, the maximum stress in Cowper–Symonds material model considering strain rate effect is significantly lower than that in linear elastic material model, and the location of maximum stress is different. When the temperature is −45, 23 or 60 °C, low silver lead-free solder Sn0.3Ag0.7Cu shows temperature softening effect obviously. Under low temperature, stress is concentrated at the interface of solder, while under normal temperature or high temperature the phenomenon is different obviously. Additionally, compared with high silver solder, low silver solder has better resistance to drop at room temperature or under working conditions.

Signal Transmission Analysis of Burn-In Socket for Fine-Pitch Ball Grid Array Package

Signal transmission analysis is investigated for a burn-in socket of fine-pitch ball grid array (FBGA) package using a three-dimensional electromagnetic field simulation. The effects of different signal-ground pin assignments on its signal transmission characteristics are analyzed in this work. Also, its electric and magnetic fields are presented to evaluated their distribution intensity around the signal and ground pins. Its reflection and insertion losses are calculated to analyze the effects of the increase in the contact length. For a burn-in socket with a contact length of 3 mm, the 1-dB the insertion loss frequency is calculated to be 38 GHz. The calculation results for insertion loss and reflection loss show that the frequency characteristics of the burn-in socket are excellent, and that the burn-in socket is suitable for high-speed applications.

Effect of Isothermal Aging on the Long-Term Reliability of Fine-Pitch Sn–Ag–Cu and Sn–Ag Solder Interconnects With and Without Board-Side Ni Surface Finish

The combined effects on long-term reliability of isothermal aging and chemically balanced or unbalanced surface finish have been investigated for fine-pitch ball grid array packages with Sn–3.0Ag–0.5Cu (SAC305) (wt.%) and Sn–3.5Ag (SnAg) (wt.%) solder ball interconnects. Two different printed circuit board surface finishes were selected to compare the effects of chemically balanced and unbalanced structure interconnects with and without board-side Ni surface finish. NiAu/solder/Cu and NiAu/solder/NiAu interconnects were isothermally aged and thermally cycled to evaluate long-term thermal fatigue reliability. Weibull plots of the combined effects of each aging condition and each surface finish revealed lifetime for NiAu/SAC305/Cu was reduced by approximately 40% by aging at 150°C; less degradation was observed for NiAu/SAC305/NiAu. Further reduction of characteristic life-cycle number was observed for NiAu/SnAg/NiAu joints. Microstructure was studied, focusing on its evolution near the board and package-side interfaces. Different mechanisms of aging were apparent under the different joint configurations. Their effects on the fatigue life of solder joints are discussed.

Interfacial Reaction Between Sn3.0Ag0.5Cu Solder and ENEPIG for Fine Pitch BGA by Stencil Printing

In this work, solder balls in ball grid array packaging technology with the pitch of 300 μm were fabricated by stencil printing solder paste and then reflowed at high temperature. In order to evaluate the quality of solder ball after printing and reflowing processes, the mechanical performance of the joint between the solder balls and the pad was measured by shear test and the electrical resistance was tested after assembly of the substrate and printed circuit board. A comparative study of pad size on the interfacial reaction between solder paste and surface finish of electroless nickel-electroless palladium-immersion gold on the organic substrate was performed and then analyzed by observing the microstructure at the interface. Large discontinuous (Cu,Ni)6Sn5 was found at the interface of the solder with the pad size of 120 μm, while spalled (Pd,Ni)Sn4 and thin (Cu,Ni)6Sn5 layer appeared for a pad size of 140 μm. The IMC (intermetallic compounds) was determined by the residual Cu concentration, the Pd concentration in the solder, and the Ni2SnP barrier layer morphology at the interface, which were significantly influenced by the pad size. A reaction model during the reflow was proposed to illustrate the growth of the IMC and the relationship between the IMC and the pad size. With Pd concentration higher than the solubility of Pd in the solder, spalled (Pd,Ni)Sn4 took shape along the interface. The solubility of Pd was influenced by Ni concentration; however, the Ni diffusion from the substrate was largely dependent on the barrier layer Ni2SnP. Furthermore, the Ni diffusion also impacted the growth and morphology of (Cu,Ni)6Sn5, which was not only limited by the Cu concentration.