Abstract

SummaryIn recent years, the electronic industries tend to offer products with smaller scales, lower cost, larger storage space and integration of various functions. The development of redistributed chip package (RCP) technology is facilitated to reduce package size for three‐dimensional integration and to enhance packaging capability for miniature requirements. Meanwhile, the logic unit is required to be combined with the memory unit to achieve miniaturization and system integration.The RCP with package on package (PoP) is constructed by stacking the RCP for the very fine pitch ball grid array at topside and the stack package ball grid array (SPBGA) at bottom side. The finite element software ANSYS is adopted in this study using the Global/Local modeling approach. The reliability of the RCP with PoP is subjected to a thermal cycle test of ‐40‐125 °C based on JEDEC specification. The Coffin‐Manson strain‐based model and the Morrow energy‐based model are employed for prediction of package fatigue life, in which the SAC387 (95.5Sn3.8Ag0.7Cu) solder joints are treated as viscoplastic behavior according to the Anand constitutive model. The other materials are modeled as elastic behavior.To investigate the solder joint reliability for the stacked package design, a numerical experiment by means of the single factor analysis is first conducted for investigation. The material factors such as Young's Modulus and coefficient of thermal expansion, the geometric factors such as component thickness are evaluated. Accordingly, the significant factors are filtered and analyzed by the Taguchi method to obtain the optimal combination. As a result, the optimal design increases package fatigue life, which contributes a significant improvement by up to 86.5% when comparing with the original model.Copyright © 2014 John Wiley & Sons, Ltd.

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